Abstract: Provided is a method for transmitting control information through an uplink by a terminal of a wireless communication system. The terminal generates a first bit stream for first control information and a second bit stream for second control information, determines the transmission power of the first bit stream and the second bit stream on the basis of the weight of the first control information with respect to the second control information, generates the multiplexed bit stream by multiplexing the first bit stream and the second bit stream, and transmits the multiplexed bit stream to a base station on the basis of the transmission power.

Abstract: Provided are a method and apparatus for transmitting an uplink control signal in a wireless communication system. A terminal receives one antenna port in a good channel state or one indicator that indicates precoding, which is selected by a base station, from the base station; and transmits the uplink control signal through a physical uplink control channel (PUCCH) to the selected one antenna port or the selected one precoding.

Abstract: Disclosed is array substrate including a pixel region having a switching region, a driving region and a storage region. A switching TFT in the switching region includes a first gate electrode, a first gate insulating layer, a switching active layer on the first gate insulating layer, a switching source electrode on a first switching ohmic contact layer, and a switching drain electrode on a second switching ohmic contact layer; a driving TFT in the driving region is connected to the switching TFT and includes a first gate electrode, a second gate insulating layer, a driving active layer on the second gate insulating layer, a driving source electrode on a first driving ohmic contact layer, and a driving drain electrode on a second driving ohmic contact layer; wherein at least one of the switching and driving TFTs further includes a second gate electrode over the switching or driving active layers.

Abstract: A method and apparatus for transmitting an expanding request in a wireless communication system is provided. A first cell transmits an expanding request, which includes a cell off state indication which indicates the first cell is going to be turned off, and a cell off timer, to a second cell, receives an expanding request acknowledge as a response to the expanding request from the second cell, and turns off power. Alternatively, a method and apparatus for transmitting a shrinking request in a wireless communication system is provided. The first cell transmits a shrinking request, which includes a cell on state indication which indicates the first cell is going to be turned on, and a cell on timer, to a second cell, receives a shrinking request acknowledge as a response to the shrinking request from the second cell, and turns on power.

Abstract: A method and apparatus for switching a connection in a wireless communication system is provided. A source cell decides radio resource control (RRC) connection switching to a target cell, transmits an aggregated user equipment (UE) context transfer message to the target cell, and transmits an RRC connection switching message to a UE in coverage of the source cell. The RRC connection switching message includes information on an identity of the target cell and a period during which the UE should finish the RRC connection switching to the target cell.

Abstract: Provided are a method and an apparatus for performing random access in a wireless communication system. A terminal receives from a base station a physical downlink control channel (PDCCH) indication, which indicates an initiation of the random access with respect to a secondary cell (SCell), based on whether a cross-carrier scheduling is supported by the SCell; transmits a physical random access channel (PRACH) preamble to the base station through the SCell; and transmits a RACH response as a response to the PRACH preamble, based on whether the SCell supports the cross-carrier scheduling, wherein the SCell and a primary cell (PCell) comprises a carrier aggregation (CA) system, the PCell is a cell from which the terminal performs radio resource control (RRC) connection with the base station, and wherein the SCell is at least one cell from residual cells in the carrier aggregation excluding the PCell.

Abstract: Provided are a method and device for acquiring a PUCCH (physical uplink control channel) resource index in a wireless communication system. A terminal acquires a PUCCH resource index indicating a dynamic PUCCH region corresponding to an e-PDCCH (enhanced physical downlink control channel). The PUCCH resource index is acquired based on the smallest CCE (control channel element) index wherein the e-PDCCH is allocated, and a first dynamic PUCCH region corresponding to the e-PDCCH is not overlapped with the dynamic PUCCH region corresponding to PDCCH.

Abstract: Provided are a method and an apparatus for determining transmission power of a preamble in a wireless communication system. A terminal estimates secondary cell (SCell) path loss with respect to a downlink (DL) component carrier (CC), which is in a linkage relationship with an uplink (UL) component carrier inside the SCell; decides the transmission power of a physical random access channel (PRACH) preamble based on the SCell path loss that is estimated; and transmits the PRACH preamble to a base station through the ULCC inside the SCell, based on the transmission power that is decided.

Abstract: There is provided a multilayer ceramic electronic component. The multilayer ceramic electronic component includes: a ceramic body including a dielectric layer; first and second internal electrodes disposed to face each other, having the dielectric layer interposed therebetween in the ceramic body; external electrodes formed on external surfaces of the ceramic body and electrically connected to the first and second internal electrodes; and grooves formed in at least one of top and bottom surface of the ceramic body on which the external electrodes are formed.

Abstract: There is provided a multi-layer ceramic electronic component including: a ceramic sintered body in which a plurality of dielectric layers are laminated; first and second internal electrodes formed in the ceramic sintered body; first and second external electrodes formed on both ends of the ceramic sintered body while covering a circumference thereof, and electrically connected to the first and second internal electrodes; and a sealing part including a glass component and formed in a gap between an outer surface of the ceramic sintered body and ends of the first and second external electrodes.

Abstract: A method for uplink synchronization in a distributed antenna system is provided. A user equipment determines a transmission offset based on a transmission point for uplink synchronization, allocates uplink synchronization signal to a second communication channel based on the transmission offset, and transmits the uplink transmission signal to the transmission point for uplink synchronization through the second communication channel.

Abstract: A method of fabricating an array substrate for a display device includes: forming a buffer layer on a substrate having a pixel region; sequentially forming a gate electrode of impurity-doped polycrystalline silicon, a gate insulating layer and an active layer of intrinsic polycrystalline silicon on the buffer layer in the pixel region; forming an interlayer insulating layer of an inorganic insulating material on the active layer; sequentially forming a source barrier pattern, a source ohmic contact layer and a source electrode on the interlayer insulating layer, sequentially forming a drain barrier pattern, a drain ohmic contact layer and a drain electrode on the interlayer insulating layer, and sequentially forming a first dummy pattern, a second dummy pattern and a data line on the interlayer insulating layer; forming a first passivation layer on a surface of the interlayer insulating layer including the source electrode, the drain electrode and the data line formed thereon; forming a gate line on the first

Abstract: A multilayer ceramic capacitor is provided. In the multilayer ceramic capacitor, a plurality of first and second inner electrodes are formed inside a ceramic sintered body. Ends of the first and second inner electrodes are alternately exposed to both ends of the ceramic sintered body. First and second outer electrodes are formed on both ends of the ceramic sintered body and connected to the first and second inner electrodes. The first and second outer electrodes include a first region having a porosity in the range of 1% to 10%, and a second region having a porosity less than that of the first region.

Abstract: There are provided a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor according to the embodiment of the present invention includes a capacitor body in which inner electrodes including a first electrode material and dielectric layers are alternately stacked; a diffusion barrier layer formed on an outer surface of the capacitor body to be electrically connected to the inner electrodes, including the first electrode material, and having a thickness of 1 ?m to 10 ?m; and a first outer electrode layer formed to cover the diffusion barrier layer and including a second electrode material having a lower reactivity to oxygen than the first electrode material.

Abstract: Disclosed is a method of fabricating a display device that includes forming a buffer layer; forming a gate electrode of extrinsic polycrystalline silicon, a gate insulating layer, an active layer of intrinsic polycrystalline silicon and an auxiliary active layer of intrinsic amorphous silicon on the buffer layer; forming an ohmic contact layer of extrinsic amorphous silicon and contacting the auxiliary active layer, source and drain electrodes and a data line; patterning a first passivation layer, an insulating interlayer and the gate insulating layer to form a gate contact hole exposing the gate electrode; forming a gate line on the first passivation layer, made of a metal material, and contacting the gate electrode through the gate contact hole; forming a second passivation layer on the gate line; patterning the first and second passivation layers to form a drain contact hole exposing the drain electrode; and forming a pixel electrode on the second passivation layer in the pixel region and contacting the dr

Abstract: A method of manufacturing an organic electroluminescent display device includes forming a first electrode on a first substrate including a plurality of pixel regions; forming a patterned spacer on the first electrode in the pixel region; forming an organic light emitting layer on the first electrode in the pixel region and on the patterned spacer; forming a second electrode on the organic light emitting layer; forming a calcium oxide layer on the second electrode; forming a moisture-absorbing layer on the calcium oxide layer; forming a driving thin film transistor on a second substrate; and forming a connection electrode connected to the driving thin film transistor, the connection electrode contacting the second electrode on the patterned spacer.

Abstract: A multilayer ceramic capacitor is provided. In the multilayer ceramic capacitor, a plurality of first and second inner electrodes are formed inside a ceramic sintered body. Ends of the first and second inner electrodes are alternately exposed to both ends of the ceramic sintered body. First and second outer electrodes are formed on both ends of the ceramic sintered body and connected to the first and second inner electrodes. The first and second outer electrodes include a first region having a porosity in the range of 1% to 10%, and a second region having a porosity less than that of the first region.

Abstract: Disclosed is a multilayer ceramic capacitor. The multilayer ceramic capacitor includes a sintered ceramic body, a plurality of first internal electrodes and a plurality of second internal electrodes formed inside the sintered ceramic body, the first and second internal electrodes having ends alternately and respectively exposed to side surfaces of the sintered ceramic body, and first and second external electrodes formed on the side surfaces of the ceramic body and electrically connected to the first and second internal electrodes, the first and second external electrodes each including a plurality of pores with an average pore size of 2 ?m to 5 ?m and having a porosity of 2% to 10%.

Abstract: Disclosed is array substrate including a pixel region having a switching region, a driving region and a storage region. A switching TFT in the switching region includes a first gate electrode, a first gate insulating layer, a switching active layer on the first gate insulating layer, a switching source electrode on a first switching ohmic contact layer, and a switching drain electrode on a second switching ohmic contact layer; a driving TFT in the driving region is connected to the switching TFT and includes a first gate electrode, a second gate insulating layer, a driving active layer on the second gate insulating layer, a driving source electrode on a first driving ohmic contact layer, and a driving drain electrode on a second driving ohmic contact layer; wherein at least one of the switching and driving TFTs further includes a second gate electrode over the switching or driving active layers.

Abstract: Disclosed is a method of fabricating a display device that includes forming a buffer layer; forming a gate electrode of extrinsic polycrystalline silicon, a gate insulating layer, an active layer of intrinsic polycrystalline silicon and an auxiliary active layer of intrinsic amorphous silicon on the buffer layer; forming an ohmic contact layer of extrinsic amorphous silicon and contacting the auxiliary active layer, source and drain electrodes and a data line; patterning a first passivation layer, an insulating interlayer and the gate insulating layer to form a gate contact hole exposing the gate electrode; forming a gate line on the first passivation layer, made of a metal material, and contacting the gate electrode through the gate contact hole; forming a second passivation layer on the gate line; patterning the first and second passivation layers to form a drain contact hole exposing the drain electrode; and forming a pixel electrode on the second passivation layer in the pixel region and contacting the dr