Patents by Inventor Hyoung-Joon Kim

Hyoung-Joon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10908461
    Abstract: The exemplary embodiments relate generally to a display device that may include: a first substrate and a second substrate, each including a transparent encapsulation area; an outer sealant along a side of the transparent encapsulation area; a pattern part disposed on the first substrate and extending in a direction parallel to the outer sealant; and a transparent sealant adjacent to the pattern part and extending in a direction parallel to the pattern part, and a manufacturing method thereof.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyoung-Joon Kim, Hyo Jin Kim, Kap Soo Yoon, Jeong Hyun Lee, Tae Hee Lee, So Young Jun, Soong Won Cho, Jeong Uk Heo
  • Patent number: 10892227
    Abstract: A fan-out semiconductor package is provided. A semiconductor chip is disposed in a through hole of a first connection member. At least a portion of the semiconductor chip is encapsulated by an encapsulant. A second connection member including a redistribution layer is formed on an active surface of the semiconductor chip. An external connection terminal having excellent reliability is formed on the encapsulant.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: January 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyoung Joon Kim, Doo Hwan Lee
  • Publication number: 20210002682
    Abstract: The present disclosure relates to modified homoserine dehydrogenase and a method for producing a homoserine-derived L-amino acid using the same.
    Type: Application
    Filed: May 21, 2019
    Publication date: January 7, 2021
    Inventors: Hyo Jin KIM, Lan HUH, Sang Jo LIM, Hyun Ah KIM, Hyoung Joon KIM, Chang il SEO, Seung Bin LEE, Ji Sun LEE
  • Patent number: 10886230
    Abstract: A fan-out semiconductor package is provided. A semiconductor chip is disposed in a through hole of a first connection member. At least a portion of the semiconductor chip is encapsulated by an encapsulant. A second connection member including a redistribution layer is formed on an active surface of the semiconductor chip. An external connection terminal having excellent reliability is formed on the encapsulant.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyoung Joon Kim, Doo Hwan Lee
  • Patent number: 10818621
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a passivation layer disposed on the second interconnection member; and an under-bump metal layer including an external connection pad formed on the passivation layer and a plurality of vias connecting the external connection pad and the redistribution layer of the second interconnection member to each other, wherein the first interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chi
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Hwan Lee, Hyoung Joon Kim, Dae Jung Byun
  • Publication number: 20200335460
    Abstract: A semiconductor package includes a semiconductor chip, an encapsulant, and an interconnection member. The semiconductor chip has connection pads. The encapsulant encapsulates a portion of the semiconductor chip. The interconnection member includes a first insulating layer disposed on the encapsulant and a portion of the semiconductor chip, a redistribution layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and the redistribution layer. The redistribution layer is electrically connected to the connection pads of the semiconductor chip, and a thickness of the second insulating layer is greater than a thickness of the first insulating layer.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Hwan LEE, Jong Rip Kim, Hyoung Joon Kim, Jin Yul Kim, Kyung Seob OH
  • Patent number: 10741461
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyoung Joon Kim, Kyung Seob Oh, Kyoung Moo Harr
  • Patent number: 10714437
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Hwan Lee, Jong Rip Kim, Hyoung Joon Kim, Jin Yul Kim, Kyung Seob Oh
  • Patent number: 10622322
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, the semiconductor chip having an active surface with connection pads disposed thereon and the semiconductor chip having an inactive surface opposing the active surface, an encapsulant, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein the first connection member and the second connection member include redistribution layers electrically connected to the connection pads, wherein the semiconductor chip includes a first passivation layer disposed on the active surface and the semiconductor chip includes a second passivation layer disposed on the first passivation layer, and wherein the redistribution layer of the second connection member is directly formed on one surface of the second passivation layer and extends onto one surface of the first connection member.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyoung Joon Kim, Doo Hwan Lee, Kyoung Moo Harr, Kyung Seob Oh
  • Patent number: 10600748
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Hwan Lee, Jong Rip Kim, Hyoung Joon Kim, Jin Yul Kim, Kyung Seob Oh
  • Patent number: 10566289
    Abstract: A fan-out semiconductor package may include: a first connection member having a through hole; a semiconductor chip disposed in the through hole and having an active surface on which a connection pad is disposed and a non-active surface opposing the active surface; an encapsulant at least partially encapsulating the first connection member and the non-active surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad, wherein the first connection member includes a first insulating layer, a first redistribution layer embedded in the first insulating layer while contacting the second connection member, and a second redistribution layer disposed on the other side of the first insulating layer opposing one side thereof in which the first redistribution layer is embedded.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Hwan Lee, Kyung Seob Oh, Jong Rip Kim, Hyoung Joon Kim
  • Patent number: 10534206
    Abstract: A liquid crystal display, including: a liquid crystal panel; and a visual inspection unit positioned in an outer region of the liquid crystal panel and transferring a test signal to the liquid crystal panel, in which the visual inspection unit includes: a test pad to which a test signal is applied; a first test line connected to the test pad; and a second test line connected to the test pad through a bridge line.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: January 14, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Jae Jeon, Yun Hee Kwak, Hyoung-joon Kim, Jae Ho Choi, Kyung Hyun Kim, Jong Woong Chang
  • Publication number: 20200004054
    Abstract: A liquid crystal display includes a first substrate including: a display area including a plurality of pixels on the first substrate, a non-display area which is disposed on an outside of the display area and in which a dummy wire is disposed on the first substrate, and an image input hole which is defined therein in the non-display area and in which an image input device is disposed, a second substrate facing the first substrate and including a display area and a non-display area corresponding to those of the first substrate, a liquid crystal layer interposed between the first and second substrates, and a sealant which is in the non-display area of the first and second substrates and seals the liquid crystal layer between the first and second substrates. The dummy wire is disposed near the image input hole.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 2, 2020
    Inventors: Tae Hee LEE, Hyoung Joon KIM, Hyo Jin KIM, Kap Soo YOON, Jeong Uk HEO, Ji Yun HONG
  • Publication number: 20190377209
    Abstract: The exemplary embodiments relate generally to a display device that may include: a first substrate and a second substrate, each including a transparent encapsulation area; an outer sealant along a side of the transparent encapsulation area; a pattern part disposed on the first substrate and extending in a direction parallel to the outer sealant; and a transparent sealant adjacent to the pattern part and extending in a direction parallel to the pattern part, and a manufacturing method thereof.
    Type: Application
    Filed: July 18, 2019
    Publication date: December 12, 2019
    Inventors: Hyoung-Joon KIM, Hyo Jin KIM, Kap Soo YOON, Jeong Hyun LEE, Tae Hee LEE, So Young JUN, Soong Won CHO, Jeong Uk HEO
  • Patent number: 10473985
    Abstract: A display apparatus includes a first substrate, a color filter, a gap maintaining pattern, a column spacer, and a blocking dam. The first substrate includes a display area and a peripheral area surrounding the display area. The color filter is disposed in the display area. The gap maintaining pattern is disposed in the peripheral area in a same layer as the color filter. The column spacer is disposed on the color filter. The blocking dam is disposed in a same layer as the column spacer and overlaps the gap maintaining pattern. The difference between the gap of the first and second substrates in the display area and the gap of the first and second substrates in the peripheral area may be decreased.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: November 12, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyoung-Joon Kim, Sijin Kim, Hyangyul Kim, Matthew Smith, Jae Hoon Jung, Moon-Keun Choi, Seungjoo Choi
  • Patent number: 10437113
    Abstract: A liquid crystal display includes a first substrate including: a display area including a plurality of pixels on the first substrate, a non-display area which is disposed on an outside of the display area and in which a dummy wire is disposed on the first substrate, and an image input hole which is defined therein in the non-display area and in which an image input device is disposed, a second substrate facing the first substrate and including a display area and a non-display area corresponding to those of the first substrate, a liquid crystal layer interposed between the first and second substrates, and a sealant which is in the non-display area of the first and second substrates and seals the liquid crystal layer between the first and second substrates. The dummy wire is disposed near the image input hole.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: October 8, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Tae Hee Lee, Hyoung Joon Kim, Hyo Jin Kim, Kap Soo Yoon, Jeong Uk Heo, Ji Yun Hong
  • Patent number: 10394086
    Abstract: The exemplary embodiments relate generally to a display device that may include: a first substrate and a second substrate, each including a transparent encapsulation area; an outer sealant along a side of the transparent encapsulation area; a pattern part disposed on the first substrate and extending in a direction parallel to the outer sealant; and a transparent sealant adjacent to the pattern part and extending in a direction parallel to the pattern part, and a manufacturing method thereof.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyoung-Joon Kim, Hyo Jin Kim, Kap Soo Yoon, Jeong Hyun Lee, Tae Hee Lee, So Young Jun, Soong Won Cho, Jeong Uk Heo
  • Patent number: 10224288
    Abstract: A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: March 5, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyung Seob Oh, Kyoung Moo Harr, Doo Hwan Lee, Seung Chul Oh, Hyoung Joon Kim, Yoon Suk Cho
  • Patent number: 10211149
    Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on an active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, a fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region, and the second line portion at least passes through a boundary between the fan-in region and the fan-out region.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kyoung Moo Harr, Kyung Seob Oh, Hyoung Joon Kim
  • Patent number: D861709
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyoung-joon Kim