Abstract: Disclosed are a composition for the prophylaxis of new influenza A (H1N1) virus infection comprising a ginkgo extract, an air filter coated with the same, and an air cleaner comprising the air filter. Having high inhibitory activity against new influenza A (H1N1) virus, the composition comprising a ginkgo extract can be applied to the prevention of new influenza A (H1N1) virus infection. Also, the filter coated with the composition can remove influenza A (H1N1) virus from the air so that it can be employed in an air cleaner for the prophylaxis of new influenza A (H1N1) virus infection.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a plug on a semiconductor substrate, forming an insulation layer over the semiconductor substrate having the plug formed thereon, defining a line type trench through a first etching of a partial thickness of the insulation layer; and defining a contact hole through a second etching of a portion of the insulation layer corresponding to the bottom of the trench so as to expose the plug.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a plug on a semiconductor substrate, forming an insulation layer over the semiconductor substrate having the plug formed thereon, defining a line type trench through a first etching of a partial thickness of the insulation layer; and defining a contact hole through a second etching of a portion of the insulation layer corresponding to the bottom of the trench so as to expose the plug.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a plug on a semiconductor substrate, forming an insulation layer over the semiconductor substrate having the plug formed thereon, defining a line type trench through a first etching of a partial thickness of the insulation layer; and defining a contact hole through a second etching of a portion of the insulation layer corresponding to the bottom of the trench so as to expose the plug.

Abstract: A multi-bit phase-change memory device includes a semiconductor substrate with a plurality of phase-change patterns sequentially stacked above the semiconductor substrate. Each phase-change pattern crosses another phase change pattern, and each phase change pattern includes a phase-change conductive line formed on a surface thereof. Bipolar transistors are installed between the semiconductor substrate and the lowermost phase-change pattern and also among the phase-change patterns, and the bipolar transistors selectively form electrical connections between the semiconductor substrate and the lowermost phase-change pattern and also among the phase-change patterns. Heating electrodes are aligned between the respective bipolar transistors and phase-change patterns. The semiconductor substrate includes an active area that extends in a direction that is perpendicular to the extension direction of the lowermost phase-change pattern.

Abstract: Example embodiments are directed to an apparatus and method for enhancing an image. The method may include extracting contrast data from color image data, generating low resolution image data and band pass image data from the contrast data using a Laplacian pyramid, generating global brightness enhanced image data from the low resolution image data to enhance an overall brightness, generating local contrast ratio enhanced image data from the band pass image data to enhance a local contrast, and/or generating enhanced contrast data from the global brightness enhanced image data and the local contrast ratio enhanced data. The apparatus may include circuitry for performing similar operations.

Abstract: Disclosed herein is a technique for manufacturing a superconducting tape grown epitaxially by a replication process. According to the technique, a long superconducting tape can be manufactured using a loop-shaped base. Further disclosed is a method for manufacturing a metal oxide device which comprises the steps of forming a solvent-soluble separation layer on a base having a single crystal or textured surface, forming a superconducting layer on the separation layer, forming a support layer on the superconducting layer, and removing the separation layer by dissolution in a solvent. According to the method, it is possible to manufacture a superconducting tape consisting of the superconducting layer and the support layer separated from the bath, and having the same crystallinity as that of the base (replication).

Abstract: Semiconductor devices having scalable two transistor memory cells, and methods of fabricating the same, are disclosed. The semiconductor devices include a semiconductor substrate having first, second and third isolation layers thereon. The first and second isolation layers are spaced apart to define a first active region therebetween, and the second and third isolation layers are likewise spaced apart to form a second active region therebetween. A cell gate is provided on each active region that includes a gate dielectric layer, a storage node, a multiple tunnel junction barrier and a source layer that are sequentially stacked. The device also includes first and second control lines that surround at least a portion of each sidewall of the cell gates. A dielectric layer may be interposed between the sidewalls of the cell gates and the control line that surrounds it. A data line connects to the cell gates.

Abstract: Ferroelectric capacitors include a support insulating film on an integrated circuit substrate and having a trench therein. A lower electrode is on sidewalls and a bottom surface of the trench. A seed conductive film covers the lower electrode. A ferroelectric film is provided on the support insulating film and the seed conductive film and an upper electrode is provided on the ferroelectric film. The lower electrode may fill the trench and the ferroelectric film may extend over all of the seed conductive film and the support insulating film adjacent the seed conductive film.

Abstract: An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

Abstract: Disclosed herein is a technique for manufacturing a superconducting tape grown epitaxially by a replication process. According to the technique, a long superconducting tape can be manufactured using a loop-shaped base. Further disclosed is a method for manufacturing a metal oxide device which comprises the steps of forming a solvent-soluble separation layer on a base having a single crystal or textured surface, forming a superconducting layer on the separation layer, forming a support layer on the superconducting layer, and removing the separation layer by dissolution in a solvent. According to the method, it is possible to manufacture a superconducting tape consisting of the superconducting layer and the support layer separated from the bath, and having the same crystallinity as that of the base (replication).

Abstract: The present invention provides methods of fabricating integrated circuit devices that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Abstract: Semiconductor devices having scalable two transistor memory cells, and methods of fabricating the same, are disclosed. The semiconductor devices include a semiconductor substrate having first, second and third isolation layers thereon. The first and second isolation layers are spaced apart to define a first active region therebetween, and the second and third isolation layers are likewise spaced apart to form a second active region therebetween. A cell gate is provided on each active region that includes a gate dielectric layer, a storage node, a multiple tunnel junction barrier and a source layer that are sequentially stacked. The device also includes first and second control lines that surround at least a portion of each sidewall of the cell gates. A dielectric layer may be interposed between the sidewalls of the cell gates and the control line that surrounds it. A data line connects to the cell gates.

Abstract: Semiconductor devices having scalable two transistor memory cells, and methods of fabricating the same, are disclosed. The semiconductor devices include a semiconductor substrate having first, second and third isolation layers thereon. The first and second isolation layers are spaced apart to define a first active region therebetween, and the second and third isolation layers are likewise spaced apart to form a second active region therebetween. A cell gate is provided on each active region that includes a gate dielectric layer, a storage node, a multiple tunnel junction barrier and a source layer that are sequentially stacked. The device also includes first and second control lines that surround at least a portion of each sidewall of the cell gates. A dielectric layer may be interposed between the sidewalls of the cell gates and the control line that surrounds it. A data line connects to the cell gates.

Abstract: The present invention provides methods of fabricating integrated circuit devices that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Abstract: Semiconductor devices having scalable two transistor memory cells, and methods of fabricating the same, are disclosed. The semiconductor devices include a semiconductor substrate having first, second and third isolation layers thereon. The first and second isolation layers are spaced apart to define a first active region therebetween, and the second and third isolation layers are likewise spaced apart to form a second active region therebetween. A cell gate is provided on each active region that includes a gate dielectric layer, a storage node, a multiple tunnel junction barrier and a source layer that are sequentially stacked. The device also includes first and second control lines that surround at least a portion of each sidewall of the cell gates. A dielectric layer may be interposed between the sidewalls of the cell gates and the control line that surrounds it. A data line connects to the cell gates.

Abstract: Ferroelectric capacitors include a support insulating film on an integrated circuit substrate and having a trench therein. A lower electrode is on sidewalls and a bottom surface of the trench. A seed conductive film covers the lower electrode. A ferroelectric film is provided on the support insulating film and the seed conductive film and an upper electrode is provided on the ferroelectric film. The lower electrode may fill the trench and the ferroelectric film may extend over all of the seed conductive film and the support insulating film adjacent the seed conductive film.

Abstract: An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

Abstract: The present invention provides methods of fabricating integrated circuit devices that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Abstract: An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.