Abstract: A liquid crystal display includes a first substrate including: a display area including a plurality of pixels on the first substrate, a non-display area which is disposed on an outside of the display area and in which a dummy wire is disposed on the first substrate, and an image input hole which is defined therein in the non-display area and in which an image input device is disposed, a second substrate facing the first substrate and including a display area and a non-display area corresponding to those of the first substrate, a liquid crystal layer interposed between the first and second substrates, and a sealant which is in the non-display area of the first and second substrates and seals the liquid crystal layer between the first and second substrates. The dummy wire is disposed near the image input hole.

Abstract: The exemplary embodiments relate generally to a display device that may include: a first substrate and a second substrate, each including a transparent encapsulation area; an outer sealant along a side of the transparent encapsulation area; a pattern part disposed on the first substrate and extending in a direction parallel to the outer sealant; and a transparent sealant adjacent to the pattern part and extending in a direction parallel to the pattern part, and a manufacturing method thereof.

Abstract: A display apparatus includes a first substrate, a color filter, a gap maintaining pattern, a column spacer, and a blocking dam. The first substrate includes a display area and a peripheral area surrounding the display area. The color filter is disposed in the display area. The gap maintaining pattern is disposed in the peripheral area in a same layer as the color filter. The column spacer is disposed on the color filter. The blocking dam is disposed in a same layer as the column spacer and overlaps the gap maintaining pattern. The difference between the gap of the first and second substrates in the display area and the gap of the first and second substrates in the peripheral area may be decreased.

Abstract: A liquid crystal display includes a first substrate including: a display area including a plurality of pixels on the first substrate, a non-display area which is disposed on an outside of the display area and in which a dummy wire is disposed on the first substrate, and an image input hole which is defined therein in the non-display area and in which an image input device is disposed, a second substrate facing the first substrate and including a display area and a non-display area corresponding to those of the first substrate, a liquid crystal layer interposed between the first and second substrates, and a sealant which is in the non-display area of the first and second substrates and seals the liquid crystal layer between the first and second substrates. The dummy wire is disposed near the image input hole.

Abstract: The exemplary embodiments relate generally to a display device that may include: a first substrate and a second substrate, each including a transparent encapsulation area; an outer sealant along a side of the transparent encapsulation area; a pattern part disposed on the first substrate and extending in a direction parallel to the outer sealant; and a transparent sealant adjacent to the pattern part and extending in a direction parallel to the pattern part, and a manufacturing method thereof.

Abstract: A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.

Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on an active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, a fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region, and the second line portion at least passes through a boundary between the fan-in region and the fan-out region.

Abstract: A display device includes a first substrate having a first lower column spacer disposed in a peripheral area, extending in a direction, and including first and second opposing slanted sides, a second substrate opposing the first substrate, the second substrate including a first upper column spacer disposed in the first peripheral area, extending in the same direction, including a slanted side, and disposed adjacent to the first side of the first lower column spacer, and a second upper column spacer having substantially a same shape as the first upper column spacer and disposed adjacent to the second side of the first lower column spacer, where the first peripheral area is disposed outside a display area of the display device.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.

Abstract: A printed circuit board including a circuit board having a cavity between an upper surface of the circuit board and a lower surface of the circuit board that are substantially parallel to each other, and a connection board including insulating layers substantially parallel with metal layers, the metal layers including metal patterns. The connection board is disposed in the cavity with the insulating layers and the metal layers of the connection board substantially perpendicular to the upper and lower surfaces of the circuit board.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.

Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on an active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, a fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region, and the second line portion at least passes through a boundary between the fan-in region and the fan-out region.

Abstract: A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member disposed on the active surface of the semiconductor chip. The connection member includes a plurality of insulating layers, a plurality of redistribution layers disposed on the plurality of insulating layers, respectively, and a plurality of via layers penetrating through the plurality of insulating layers, respectively, and at least two of the plurality of insulating layers or at least two of the plurality of via layers have different thicknesses.

Abstract: A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member disposed on the active surface of the semiconductor chip. The connection member includes a plurality of insulating layers, a plurality of redistribution layers disposed on the plurality of insulating layers, respectively, and a plurality of via layers penetrating through the plurality of insulating layers, respectively, and at least two of the plurality of insulating layers or at least two of the plurality of via layers have different thicknesses.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member.

Abstract: An electronic component package and a method of manufacturing an electronic component package are provided. An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity, a redistribution layer disposed adjacent to the frame and electrically connected to the electronic component, and an encapsulation material encapsulating the electronic component and having an elastic modulus smaller than that of a material constituting the frame.

Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, the semiconductor chip having an active surface with connection pads disposed thereon and the semiconductor chip having an inactive surface opposing the active surface, an encapsulant, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein the first connection member and the second connection member include redistribution layers electrically connected to the connection pads, wherein the semiconductor chip includes a first passivation layer disposed on the active surface and the semiconductor chip includes a second passivation layer disposed on the first passivation layer, and wherein the redistribution layer of the second connection member is directly formed on one surface of the second passivation layer and extends onto one surface of the first connection member.