Abstract: The present invention provide integrated circuit devices and methods of fabricating the same that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Abstract: Methods are provided for conductively contacting an integrated circuit, including a plurality of spaced apart lines thereon, using a dummy dielectric layer. A dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines.

Abstract: In the ferroelectric memory device an auxiliary polysilicon layer is formed on an interlayer insulating layer having a polysilicon contact plug formed therein. A metal silicide layer is formed on the auxiliary polysilicon layer. A capacitor structure is then formed on the metal silicide layer.

Abstract: A half-tone phase shift mask includes a transparent substrate, a phase shift pattern formed on the semiconductor substrate and having a stepped aperture which exposes the transparent substrate by a predetermined width, and an opaque film pattern formed on the upper surface of the phase shift pattern. The stepped aperture is defined by an interior side wall of the phase shift pattern. This side wall includes a horizontal surface which is parallel to the surface defining the bottom of the aperture. Light transmitted by the mask via the surface defining the bottom of the aperture has a phase difference of 180 degrees with respect to light transmitted by the mask via the horizontal surface, and light transmitted by the mask via the surface defining the bottom of the aperture has a phase difference of more than 180 degrees with respect to light transmitted by the mask via the upper surface of the phase shift pattern.

Abstract: A method for forming a conductive contact of a semiconductor device is provided. According to one aspect of the present invention, a dummy dielectric layer pattern having a dummy opening and an interdielectric layer pattern having a lower etch-rate than that of the dummy dielectric layer, for filling the dummy opening are formed on a semiconductor substrate. The dummy dielectric layer pattern using the interdielectric layer pattern as an etching mask is selectively removed, and a contact opening for exposing the semiconductor substrate of a portion in which the dummy dielectric layer pattern is located.

Abstract: The present invention provide integrated circuit devices and methods of fabricating the same that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Abstract: An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

Abstract: Methods are provided for conductively contacting an integrated circuit, including a plurality of spaced apart lines thereon, using a dummy dielectric layer. A dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines.

Abstract: A method for forming a conductive contact of a semiconductor device is provided. According to one aspect of the present invention, a dummy dielectric layer pattern having a dummy opening and an interdielectric layer pattern having a lower etch-rate than that of the dummy dielectric layer, for filling the dummy opening are formed on a semiconductor substrate. The dummy dielectric layer pattern using the interdielectric layer pattern as an etching mask is selectively removed, and a contact opening for exposing the semiconductor substrate of a portion in which the dummy dielectric layer pattern is located.

Abstract: A half-tone phase shift mask includes a transparent substrate, a phase shift pattern formed on the semiconductor substrate and having a stepped aperture which exposes the transparent substrate by a predetermined width, and an opaque film pattern formed on the upper surface of the phase shift pattern. The stepped aperture is defined by an interior side wall of the phase shift pattern. This side wall includes a horizontal surface which is parallel to the surface defining the bottom of the aperture. Light transmitted by the mask via the surface defining the bottom of the aperture has a phase difference of 180 degrees with respect to light transmitted by the mask via the horizontal surface, and light transmitted by the mask via the surface defining the bottom of the aperture has a phase difference of more than 180 degrees with respect to light transmitted by the mask via the upper surface of the phase shift pattern.

Abstract: Half-tone phase shift masks (PSM) having a high transmittance and can be easy to fabricate are provided. The half-tone PSM includes a substrate which is transparent with respect to exposure light, a phase shifter pattern formed on the transparent substrate, and a phase shifting groove which can be formed by etching the transparent substrate. Methods for fabricating half-tone PSMs are also provided. The half-tone PSM can have a higher transmittance than that of a conventional half-tone PSM, and the phase shifting groove can have a uniform surface. Thus, a fine pattern having an excellent contrast can be formed using a short wavelength.