Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: A method includes receiving an eco-cruise control request that includes a requested cruise control velocity and a velocity tolerance. The eco-cruise control request instructs an drive unit to operate a vehicle at a velocity within the velocity tolerance of the requested cruise control velocity. The method also includes determining a range of candidate cruise control velocities that satisfy the velocity tolerance of the requested cruise control velocity. The method also includes determining an eco-cruise control velocity that maximizes a drive unit efficiency of the drive unit. Here, the eco-cruise control velocity includes one of the candidate cruise control velocities from the range of candidate cruise control velocities.

Abstract: Navigation devices and methods of operation are provided. The navigation device includes a communication unit; a display; an input unit for receiving an input of data; a communication unit; and a controller for controlling operation of the display and the input unit. The controller connects to a data server through the communication unit, requests path setting information to the data server, receives the path setting information from the data server, acquires present position information of the navigation device, acquires a user moving path by reflecting the acquired position information and the received path setting information, and sets the user moving path as a guidance path. In this case, the path setting information is generated in another electronic device or the data server based on user input information input from the another electronic device.

Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: Navigation devices and methods of operation are provided. The navigation device includes a communication unit; a display; an input unit for receiving an input of data; a communication unit; and a controller for controlling operation of the display and the input unit. The controller connects to a data server through the communication unit, requests path setting information to the data server, receives the path setting information from the data server, acquires present position information of the navigation device, acquires a user moving path by reflecting the acquired position information and the received path setting information, and sets the user moving path as a guidance path. In this case, the path setting information is generated in another electronic device or the data server based on user input information input from the another electronic device.

Abstract: An impurity removal amount prediction method in chemical process is provided. The impurity removal amount prediction method in chemical process according to the embodiments of the present invention comprises making neural network models learn using data from a chemical process and predicting removal amounts of impurities removed in the chemical process using the learned neural network models. The impurities are included in the feed supplied to reactors of the chemical process and are removed by reacting with catalysts disposed in the reactors. The reactors include a first reactor and a second reactor arranged in parallel. The neural network models include a first neural network model applied to the first reactor and a second neural network model applied to the second reactor. The neural network models learn in the direction to minimize the difference between the output data of the first neural network model and the second neural network model.

Abstract: A display apparatus includes a substrate including a display area, in which a plurality of pixels are arranged, and a peripheral area outside the display area, a data line arranged in the display area and extending in a first direction, a first semiconductor pattern disposed on the data line and extending in a second direction crossing the first direction, a gate line disposed on the first semiconductor pattern and extending in the first direction to cross the first semiconductor pattern, and an anchor located at an end portion of the gate line and having a width greater than a width of the gate line.

Abstract: A semiconductor device including a substrate and a capacitor structure arranged on the substrate. The capacitor structure includes a plurality of lower electrodes extending in a vertical direction perpendicular to a surface of the substrate and spaced apart from each other, supporters arranged between the plurality of lower electrodes, an upper electrode spaced apart from each of the plurality of lower electrodes, a dielectric layer arranged between each of the lower electrodes and the upper electrode, and a plurality of particles each in contact with the dielectric layer and arranged between each of the plurality of lower electrodes and the upper electrode.

Abstract: A substrate treating apparatus, including a process chamber having a bottom portion configured to secure a substrate while a substrate treating process is performed on the substrate; and a dielectric window arranged at an upper portion of the process chamber to define a process space, and including: an insulative body, an antenna disposed on an upper surface of the insulative body, a protection layer disposed on a lower surface of the insulative body, and an etch resistor protruding from at least a portion of the protection layer toward the process space, wherein, based on power being applied to the antenna, a plasma is generated in the process space, and wherein the insulative body is protected from the plasma by the protection layer and the etch resistor.

Abstract: A method of manufacturing, by atomic layer deposition, an electrode including a perovskite type crystal structure represented by Formula 1, includes: forming a vanadium-containing precursor on a substrate; forming a vanadium-containing intermediate phase by reacting the vanadium-containing precursor with oxygen molecules; and forming a first thin film by reacting the vanadium-containing intermediate phase with water. wherein, in Formula 1, 0.3?x?0.7, and 2.5?y?3.0.

Abstract: A light-emitting device and an electronic apparatus including the same.

Abstract: A display device includes: a buffer layer including an inorganic insulating material, an active pattern disposed on the buffer layer and including a channel region and a first conductor region adjacent to the channel region, a gate insulating layer disposed on the buffer layer and the active pattern and including an inorganic insulating material, a gate electrode layer including a first electrode extending along a side surface of the gate insulating layer and including a first contact portion electrically contacting the first conductor region, and an oxygen supply layer including a first pattern disposed between the first electrode and the gate insulating layer, wherein the first pattern includes a first groove recessed from a side surface of to surround at least a part of the first contact portion in a plan view.

Abstract: A light-emitting device and an electronic apparatus including the light-emitting device. The light-emitting device includes a first electrode, a second electrode, and an interlayer arranged between the first electrode and the second electrode, the interlayer includes an emission layer, the emission layer includes one or more m1 hosts, a sensitizer, and a fluorescent emitter, where m1 is an integer of 1 or more, and when m1 is 2 or more, the two or more hosts are each different from the other, the one or more m1 hosts, the sensitizer, and the fluorescent emitter are different from each other, and Expression 1 is satisfied. 0 ? debye ? ? "\[LeftBracketingBar]" PDM ? ( S ) - PDM ? ( H ) ? "\[RightBracketingBar]" ? 3 ? debye Expression ? 1 Expression 1 is the same as described in the present specification.

Abstract: A blind spot detection control apparatus for a vehicle, configured for judging whether an object detected during a detection cycle in blind spot zone of the vehicle is an alert object, for outputting a result of judgement to a warning which warns a driver of vehicle that an object is present in blind spot zone based on judging that object detected in blind spot zone is an alert object, wherein apparatus is configured to judge whether an object detected in blind spot zone is an alert object by comparing detection parameters relating to a current target object detected in blind spot zone during a current detection cycle with detection parameters relating to a reference moving object corresponding to a target object detected in blind spot zone at least during a previous detection cycle.

Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature 5 bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number 10 of digits of the addition result depending on a shift value to generate a shifted addition result and an accumulator generating output feature data based on the shifted addition result.

Abstract: A method may be used for manufacturing a semiconductor element. The method may include the following steps: preparing a substrate; forming a semiconductor layer on the substrate, wherein the semiconductor layer includes crystallized two-dimensional layers; forming a source electrode and a drain electrode on the semiconductor layer; forming an semiconductor member by wet etching the semiconductor layer using sodium hypochlorite as an etchant, wherein the wet etching results in a residue; and removing the residue using purified water and an inert gas.

Abstract: Provided are an organometallic compound represented by Formula 1 and an organic light-emitting device including the same: M1(Ln1)n1(Ln2)3-n1 ??Formula 1 wherein, in Formula 1, Ln2 is a ligand represented by Formula 1A, and other substituents are the same as described in the detailed description of the present specification:

Abstract: Provided is a voltage waveform control method comprising generating a voltage waveform of a non-sinusoidal wave comprising a pulse period having a positive bias voltage, a ramp period having a negative bias voltage, a first transition period changing from the pulse period to the ramp period, and a second transition period changing from the ramp period to the pulse period, adjusting a length of a negative voltage period having the negative bias voltage during a period of the voltage waveform to be at most 20% of a total length of the period, adjusting a slope of the ramp period, and outputting an adjusted voltage waveform based on the adjusted length of the negative voltage period and the adjusted slope of the ramp period, where the adjusting the length of the negative voltage period comprises adjusting a length of the first transition period and a length of the second transition period.

Abstract: A semiconductor device includes a first transistor on a first region of a substrate, and a second transistor on a second region of the substrate. The first transistor includes a first gate insulating layer including a first interfacial insulating layer, a first lower high-? dielectric layer, and a first composite dielectric layer, sequentially stacked on each of first semiconductor channel layers. The second transistor includes a second gate insulating layer including a second interfacial insulating layer, a second lower high-? dielectric layer, a second composite dielectric layer, and a second upper high-? dielectric layer, sequentially stacked on each of second semiconductor channel layers. The first and the second lower high-? dielectric layers include a first metal element, the second upper high-? dielectric layer includes a second metal element, and the first and the second composite dielectric layers include both of the first and the second metal elements.