Abstract: A method for generating plasma for removing metal oxide from a substrate is provided. The method includes providing a powered electrode assembly, which includes a powered electrode, a dielectric layer, and a wire mesh disposed between the powered electrode and the dielectric layer. The method also includes providing a grounded electrode assembly disposed opposite the powered electrode assembly to form a cavity wherein the plasma is generated. The wire mesh is shielded from the plasma by the dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the metal oxide. The method further includes introducing at least one inert gas and at least one process gas into the cavity. The method yet also includes applying an rf field to the cavity using the powered electrode to generate the plasma from the inert and the process gas.

Abstract: Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.

Abstract: Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.

Abstract: A method of depositing a thin film by atomic layer deposition (ALD) on a substrate surface is disclosed. The disclosed method includes placing an ALD deposition proximity head above the substrate with at least one gas channel configured to dispense a gas to an active process region of the substrate surface. The ALD deposition proximity head extends over and is being spaced apart from the active process region of the substrate surface when present. After a pulse of a first reactant gas is dispensed on the active process region of the substrate surface underneath the proximity head, a pulse of a second reactant gas is dispensed on the active process region of the substrate surface underneath the proximity head to react with the first reactant gas to form a portion of the thin layer of ALD film on the surface of substrate underneath the proximity head.

Abstract: Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: A method of depositing a thin film by atomic layer deposition (ALD) on a substrate surface is disclosed. The disclosed method includes placing an ALD deposition proximity head above the substrate with at least one gas channel configured to dispense a gas to an active process region of the substrate surface. The ALD deposition proximity head extends over and is being spaced apart from the active process region of the substrate surface when present. After a pulse of a first reactant gas is dispensed on the active process region of the substrate surface underneath the proximity head, a pulse of a second reactant gas is dispensed on the active process region of the substrate surface underneath the proximity head to react with the first reactant gas to form a portion of the thin layer of ALD film on the surface of substrate underneath the proximity head.

Abstract: Presented are methods and systems for fabricating three-dimensional integrated circuits having large diameter through-hole vias. One embodiment of the present invention provides a method of processing a wafer having holes for through-hole vias. The method comprises plating a gapfill metal on the wafer. The method also comprises chemically or electrochemically deplating a portion of the overburden metal. The method further comprises using chemical mechanical planarization to planarize the gapfill metal and to remove the remaining overburden metal. Another embodiment of the present invention is an integrated system comprising a process chamber for containing the wafer, a plating component integrated with the process chamber, and a deplating component integrated with the process chamber. The plating component is configured to electrochemically plate a gapfill metal onto the wafer to a least partially fill the holes.

Abstract: A method for generating plasma for removing an edge polymer from a substrate is provided. The method includes providing a powered electrode assembly, which includes a powered electrode, a dielectric layer, and a wire mesh disposed between the powered electrode and the dielectric layer. The method also includes providing a grounded electrode assembly disposed opposite the powered electrode assembly to form a cavity wherein the plasma is generated. The wire mesh is shielded from the plasma by the dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the edge polymer. The method further includes introducing at least one inert gas and at least one process gas into the cavity. The method yet also includes applying an RF field to the cavity using the powered electrode to generate the plasma from the inert gas and process gas.

Abstract: An integrated system for processing a substrate in controlled environment to enable deposition of a thin copper seed layer on a surface of a metallic barrier layer of a copper interconnect is provided. The system includes a lab-ambient transfer chamber, a vacuum transfer chamber, a vacuum process module for cleaning an exposed surface of a metal oxide of a underlying metal, a vacuum process module for depositing the metallic barrier layer, and a controlled-ambient transfer chamber filled with an inert gas, wherein at least one controlled-ambient process module is coupled to the controlled-ambient transfer chamber. In addition, the system includes an electroless copper deposition process module used to deposit the thin layer of copper seed layer on the surface of the metallic barrier layer.

Abstract: The embodiments provide apparatus and methods of depositing conformal thin film on interconnect structures by providing processes and systems using an atomic layer deposition (ALD). More specifically, each of the ALD systems includes a proximity head that has a small reaction volume right above an active process region of the substrate surface. The proximity head dispenses small amount of reactants and purging gas to be distributed and pumped away from the small reaction volume between the proximity head and the substrate in relatively short periods, which increases the through-put. In an exemplary embodiment, a proximity head for dispensing reactants and purging gas to deposit a thin film by atomic layer deposition (ALD) is provided. The proximity head is configured to sequentially dispensing a reactant gas and a purging gas to deposit a thin ALD film under the proximity head. The proximity head covers an active process region of a substrate surface.

Abstract: A proximity heads for dispensing reactants and purging gas to deposit a thin film by Atomic Layer Deposition (ALD) includes a plurality of sides. Extending over a portion of the substrate region and being spaced apart from the portion of the substrate region when present, the proximity head is rotatable so as to place each side in a direction of the substrate region, and is disposed in a vacuum chamber coupled to a carrier gas source to sustain a pressure for the proximity head during operation. Each side of the proximity head includes a gas conduit through which the reactant gas and the purging gas are sequentially dispensed, and at least two separate vacuum conduits on each side of the gas conduit to pull excess reactant gas, purging gas, or deposition byproducts from a reaction volume between a surface of the proximity head facing the substrate and the substrate.

Abstract: Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve metal-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce an improved metal-to-metal interface, more specifically barrier-to-copper interface. An exemplary method of preparing a substrate surface of a substrate to deposit a metallic barrier layer to line a copper interconnect structure of the substrate and to deposit a thin copper seed layer on a surface of the metallic barrier layer in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes cleaning an exposed surface of a underlying metal to remove surface metal oxide in the integrated system, wherein the underlying metal is part of a underlying interconnect electrically connected to the copper interconnect.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: Methods for cleaning an edge of a semiconductor substrate include providing a brush in a housing, the housing provides a volume for holding the brush. A cleaning fluid is inserted into the housing to at least partially fill the volume holding the brush, with the cleaning fluid. The cleaning fluid is removed from the volume of the housing while the cleaning fluid is being inserted. The brush is rotated within the housing while the cleaning fluid is inserted and removed. The edge of the semiconductor substrate is inserted into a slot of the housing. The edge of the semiconductor substrate inserted into the slot is maintained at a distance and for a period of time. The distance is configured such that the brush contacts the edge of the semiconductor substrate but continues to enable rotation of the brush within the housing.

Abstract: The present invention relates to methods and structures for the metallization of semiconductor devices. One aspect of the present invention is a method of forming a semiconductor device having copper metallization. In one embodiment, the method includes providing a patterned wafer having a diffusion barrier for copper; depositing a copperless seed layer on the diffusion barrier effective for electrochemical deposition of gapfill copper. The seed layer is formed by a conformal deposition process and by a nonconformal deposition process. The method further includes electroplating copper gapfill onto the seed layer. Another aspect of the invention includes electronic devices made using methods and structures according to embodiments of the present invention.

Abstract: An apparatus, system and method for cleaning a substrate edge include a bristle brush unit that cleans bevel polymers deposited on substrate edges using frictional contact in the presence of cleaning chemistry. The bristle brush unit is made up of a plurality of outwardly extending vanes and is mounted on a rotating shaft. An abrasive material is distributed throughout and within the outwardly extending vanes of the bristle brush unit to provide the frictional contact. The bristle brush unit cleans the edge of the substrate by allowing frictional contact of the plurality of abrasive particles with the edge of the substrate in the presence of fluids, such as cleaning chemistry, to cut, rip and tear the bevel polymer from the edge of the substrate.

Abstract: An interconnect structure is provided, including a layer of dielectric material having at least one opening and a first barrier layer on sidewalls defining the opening. A ruthenium-containing second barrier layer overlays the first barrier layer, the second barrier layer having a ruthenium zone, a ruthenium oxide zone, and a ruthenium-rich zone. The ruthenium zone is interposed between the first barrier layer and the ruthenium oxide zone. The ruthenium oxide zone is interposed between the ruthenium zone and the ruthenium-rich zone.

Abstract: The present invention relates to methods and structures for the metallization of semiconductor devices. One aspect of the present invention is a method of forming a semiconductor device having copper metallization. In one embodiment, the method includes providing a patterned wafer having a diffusion barrier for copper; depositing a copperless seed layer on the diffusion barrier effective for electrochemical deposition of gapfill copper. The seed layer is formed by a conformal deposition process and by a nonconformal deposition process. The method further includes electroplating copper gapfill onto the seed layer. Another aspect of the invention includes electronic devices made using methods and structures according to embodiments of the present invention.

Abstract: The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition.