Abstract: An interconnect structure is provided, including a layer of dielectric material having at least one opening and a first barrier layer on sidewalls defining the opening. A ruthenium-containing second barrier layer overlays the first barrier layer, the second barrier layer having a ruthenium zone, a ruthenium oxide zone, and a ruthenium-rich zone. The ruthenium zone is interposed between the first barrier layer and the ruthenium oxide zone. The ruthenium oxide zone is interposed between the ruthenium zone and the ruthenium-rich zone.

Abstract: Methods and systems for handling a substrate through processes including an integrated electroless deposition process includes processing a surface of the substrate in an electroless deposition module to deposit a layer over conductive features of the substrate using a deposition fluid. The surface of the substrate is then rinsed in the electroless deposition module with a rinsing fluid. The rinsing is controlled to prevent de-wetting of the surface so that a transfer film defined from the rinsing fluid remains coated over the surface of the substrate. The substrate is removed from the electroless deposition module while maintaining the transfer film over the surface of the substrate. The transfer film over the surface of the substrate prevents drying of the surface of the substrate so that the removing is wet. The substrate, once removed from the electroless deposition module, is moved into a post-deposition module while maintaining the transfer film over the surface of the substrate.

Abstract: Methods of depositing a barrier layer on an interconnect structure in an atomic deposition environment are provided. One method includes depositing a barrier layer on the interconnect structure with a first nitrogen concentration during a first phase of deposition in the atomic deposition environment, The interconnect structure is formed in a dielectric layer. Then, continuing the deposition of the barrier layer on the interconnect structure with a second nitrogen concentration during a second phase deposition in the atomic deposition environment. The nitrogen concentration step-wisely decreases from the first nitrogen concentration in the first phase of the barrier layer to the second nitrogen concentration in the second phase of the barrier layer, and the first nitrogen concentration is highest where the barrier layer is in contact with the dielectric layer.

Abstract: Various embodiments provide improved processes and systems that produce a barrier layer with decreasing nitrogen concentration with the increase of film thickness. A barrier layer with decreasing nitrogen concentration with film thickness allows the end of barrier layer with high nitrogen concentration to have good adhesion with a dielectric layer and the end of barrier layer with low nitrogen concentration (or metal-rich) to have good adhesion with copper. An exemplary method of depositing a barrier layer on an interconnect structure is provided. The method includes (a) providing an atomic layer deposition environment, (b) depositing a barrier layer on the interconnect structure with a first nitrogen concentration during a first phase of deposition in the atomic layer deposition environment.

Abstract: The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition.

Abstract: An apparatus generating a plasma for removing fluorinated polymer from a substrate is provided. The apparatus includes a powered electrode assembly, which includes a powered electrode, a first dielectric layer, and a first wire mesh disposed between the powered electrode and the first dielectric layer. The apparatus also includes a grounded electrode assembly disposed opposite the powered electrode assembly so as to form a cavity wherein the plasma is generated. The first wire mesh is shielded from the plasma by the first dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the fluorinated polymer.

Abstract: The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition.

Abstract: A method for generating plasma for removing metal oxide from a substrate is provided. The method includes providing a powered electrode assembly, which includes a powered electrode, a dielectric layer, and a wire mesh disposed between the powered electrode and the dielectric layer. The method also includes providing a grounded electrode assembly disposed opposite the powered electrode assembly to form a cavity wherein the plasma is generated. The wire mesh is shielded from the plasma by the dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the metal oxide. The method further includes introducing at least one inert gas and at least one process gas into the cavity. The method yet also includes applying an rf field to the cavity using the powered electrode to generate the plasma from the inert and the process gas.

Abstract: A method for generating plasma for removing an edge polymer from a substrate is provided. The method includes providing a powered electrode assembly, which includes a powered electrode, a dielectric layer, and a wire mesh disposed between the powered electrode and the dielectric layer. The method also includes providing a grounded electrode assembly disposed opposite the powered electrode assembly to form a cavity wherein the plasma is generated. The wire mesh is shielded from the plasma by the dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the edge polymer. The method further includes introducing at least one inert gas and at least one process gas into the cavity. The method yet also includes applying an RF field to the cavity using the powered electrode to generate the plasma from the inert gas and process gas.

Abstract: An apparatus generating a plasma for removing fluorinated polymer from a substrate is disclosed. The embodiment includes a powered electrode assembly, including a powered electrode, a first dielectric layer, and a first wire mesh disposed between the powered electrode and the first dielectric layer. The embodiment also includes a grounded electrode assembly disposed opposite the powered electrode assembly so as to form a cavity wherein the plasma is generated, the first wire mesh being shielded from the plasma by the first dielectric layer when the plasma is present in the cavity, the cavity having an outlet at one end for providing the plasma to remove the fluorinated polymer.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: An apparatus generating a plasma for removing metal oxide from a substrate is disclosed. The embodiment includes a powered electrode assembly, including a powered electrode, a first dielectric layer, and a first wire mesh disposed between the powered electrode and the first dielectric layer. The embodiment also includes a grounded electrode assembly disposed opposite the powered electrode assembly so as to form a cavity wherein the plasma is generated, the first wire mesh being shielded from the plasma by the first dielectric layer when the plasma is present in the cavity, the cavity having an outlet at one end for providing the plasma to remove the metal oxide.

Abstract: An apparatus generating a plasma for removing an edge polymer from a substrate is disclosed. The embodiment includes a powered electrode assembly, including a powered electrode, a first dielectric layer, and a first wire mesh disposed between the powered electrode and the first dielectric layer. The embodiment also includes a grounded electrode assembly disposed opposite the powered electrode assembly so as to form a cavity wherein the plasma is generated, the first wire mesh being shielded from the plasma by the first dielectric layer when the plasma is present in the cavity, the cavity having an outlet at one end for providing the plasma to remove the edge polymer.

Abstract: An integrated system for depositing films on a substrate for copper interconnect is provided. The system includes a processing chamber with a plurality of proximity heads, and a vacuum transfer module coupled to the processing chamber. Selected ones of the proximity heads are used for surface treatments and atomic layer depositions (ALDs). The system further includes a processing module for copper seed layer deposition, which is integrated with a rinse/dryer to enable dry-in/dry-out process capability and is filled with an inert gas to limit the exposure of the substrate to oxygen. Additionally, the system includes a controlled-ambient transfer module coupled to the processing module for copper seed layer deposition. Further, the system includes a loadlock coupled to the vacuum transfer module and to the controlled-ambient transfer module. The integrated system enables controlled-ambient transitions within the system to limit exposure of the substrate to uncontrolled ambient conditions outside of the system.

Abstract: The embodiments fill the need enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect with good electro-migration performance and with reduced risk of stress-induce voiding of copper interconnect. Electromigration and stress-induced voiding are affected by the adhesion between the barrier layer and the copper layer. A functionalization layer is deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect. The functionalization layer forms strong bonds with barrier layer and with copper to improve adhesion property between the two layers. An exemplary method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in order to improve electromigration performance of the copper interconnect is provided.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: A method and system for depositing films on a substrate for copper interconnect in an integrated system are provided to enable controlled-ambient transitions within an integrated system to limit exposure of the substrate to uncontrolled ambient conditions. The method includes moving the substrate into a processing chamber having a plurality of proximity heads. Within the processing chamber, barrier layer deposition is performed over a surface of the substrate using one of the plurality of proximity heads functioning to perform barrier layer ALD. In addition, the method includes moving the substrate from the processing chamber, through a transfer module of the integrated systems, into a processing module for performing copper seed layer deposition. Within the processing module for performing copper seed layer deposition, copper seed layer deposition is performed over the surface of the substrate.

Abstract: A method of etching a conductive layer includes converting at least a portion of the conductive layer and etching the conductive layer to substantially remove the converted portion of the conductive layer and thereby expose a remaining surface. The remaining surface has an average surface roughness of less than about 10 nm. A system for etching a conductive layer is also disclosed.

Abstract: An apparatus, system and method for cleaning a substrate edge include a bristle brush unit that cleans bevel polymers deposited on substrate edges using frictional contact in the presence of cleaning chemistry. The bristle brush unit is made up of a plurality of outwardly extending vanes and is mounted on a rotating shaft. An abrasive material is distributed throughout and within the outwardly extending vanes of the bristle brush unit to provide the frictional contact. The bristle brush unit cleans the edge of the substrate by allowing frictional contact of the plurality of abrasive particles with the edge of the substrate in the presence of fluids, such as cleaning chemistry, to cut, rip and tear the bevel polymer from the edge of the substrate.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.