Abstract: There is provided an analog-stochastic converter for converting an analog voltage signal into a pulse signal having a corresponding probability. The analog-stochastic converter is implemented using a threshold switching element and a simple logic circuit, thereby reducing a size of the analog-stochastic converter and enabling a low power operation thereof. In addition, in order to update a weight, instead of an analog signal, a probability signal is applied using the above-described analog-stochastic converter, thereby updating a weight in a fully-parallel manner in a synaptic element array having an intersection structure. Accordingly, it is possible to shorten a time for weight update.

Abstract: A sandwich panel for an automobile includes a core layer, a surface layer, and an adhesive layer. The core layer includes glass fibers and thermoplastic resins and defines an optimal weight and thickness to provide flexural performance and non-flammability. The sandwich panel provides a flame barrier layer, which is a non-combustible layer during ignition and prevents flame from leaking to the outside of the panel.

Abstract: A semiconductor manufacturing equipment may include a process chamber for treating a substrate; a front-end module including a first transfer robot, wherein the first transfer robot may be configured to transport the substrate received in a container; a transfer chamber between the front-end module and the process chamber, wherein the transfer chamber may be configured to load or unload the substrate into or out of the process chamber; and a cassette capable of receiving a replaceable component capable of being used in the process chamber. The front-end module may include a seat plate configured to move in a sliding manner so as to retract or extend into or from the front-end module. The cassette may be configured to be loaded into the front-end module while the cassette is seated on the seat plate.

Abstract: A camera module includes: a first substrate on which an image sensor configured to convert an optical signal incident through a lens module into an electrical signal is disposed and a first connection terminal is disposed; a second substrate spaced apart from the first substrate and including a second connection terminal formed in a position facing the first connection terminal; and a terminal connector electrically connecting the first connection terminal and the second connection terminal to each other and configured to maintain a preset distance between the first substrate and the second substrate. In the camera module, the terminal connector includes: a connecting member including a first connection portion, a second connection portion, and a deformable portion; and a support member configured to maintain the preset distance between the first substrate and the second substrate.

Abstract: There is provided a substrate support device. The substrate support device includes a substrate support part on which a wafer is deposited, the substrate support part including a first mesh electrode and a second mesh electrode disposed under the first mesh electrode; a chucking circuit configured to apply a DC voltage to the first mesh electrode; and an edge control circuit configured to control timings of operations related to the first mesh electrode and the second mesh electrode and control RF (Radio Frequency). The second mesh electrode is divided into a plurality of second sub-mesh electrode to remove an induced electromotive force generated due to a closed loop.

Abstract: A weight confirmation method for analog synaptic devices of an artificial neural network includes: learning artificial neural network hardware based on artificial analog memory devices using an artificial neural network learning algorithm; after the learning of the artificial neural network hardware, reading a total weight of a pair of synaptic devices; comparing the total weight of the pair of synaptic devices with 0; applying weights to a positive synaptic device and a negative synaptic device of the pair of synaptic devices, respectively; and confirming the total weight of the pair of synaptic devices in accordance with the weight of the positive synaptic device and the weight of the negative synaptic device. A retention problem of analog synaptic devices is overcome and thus the artificial neural network may stably operate.

Abstract: A three-terminal synaptic device includes a substrate; a source electrode and a drain electrode which are provided on the substrate and spaced apart from each other. The three-terminal synaptic device further includes: a channel layer provided on the substrate, the source electrode, and the drain electrode; an ion reservoir layer which stores active ions; a gate electrode provided on the ion reservoir layer; and an ion barrier layer disposed between the ion reservoir layer. In particular, the channel layer controls movement of active ions between the ion reservoir layer and the channel layer. The three-terminal synaptic device inhibits rapid movement of ions.

Abstract: A two-terminal atom-based switching device having a fast operating speed and high durability and a manufacturing method thereof are disclosed. It is possible to reduce a forming voltage during positive voltage forming by forming an oxygen vacancy percolation path through negative voltage forming, which is first forming, and forming high binding energy and low formation energy between oxygen vacancies and metal ions implanted through positive voltage forming which is second forming after the negative voltage forming. Further, since a significant amount of metal ions implanted into the insulating layer through negative voltage application switching after the positive voltage forming is removed, the volatility of the two-terminal atom-based switching device may be improved, and a stuck-on failure phenomenon in the durability may be prevented.

Abstract: A neuromorphic hardware apparatus based on a resistive memory array includes a resistive memory array in which a plurality of synaptic resistor elements are arranged. Each synaptic resistor element is changed in its resistance value depending on a voltage pulse applied thereto and stores the resistance value for a predetermined time. The apparatus also includes a neuron circuit configured to receive an output signal from the resistive memory array and to output a voltage signal to another resistive memory array. The neuron circuit includes a temperature compensation unit, which compensates for an output voltage of the resistive memory array on the basis of an operating temperature of the resistive memory array. Even when a resistive memory array outputs an abnormal output depending on an operating temperature, by compensating a neuron circuit for an input value, it is possible to prevent an operation error from occurring.

Abstract: Disclosed are a neuromorphic device and a unit synapse devices forming the same. The unit synapse device has a learning device and an inference device. The learning device and the inference device may share a via oxide layer and a common electrode, and a learning operation and an inference operation may be performed in one unit synapse device.

Abstract: There is provided an analog-stochastic converter for converting an analog voltage signal into a pulse signal having a corresponding probability. The analog-stochastic converter is implemented using a threshold switching element and a simple logic circuit, thereby reducing a size of the analog-stochastic converter and enabling a low power operation thereof. In addition, in order to update a weight, instead of an analog signal, a probability signal is applied using the above-described analog-stochastic converter, thereby updating a weight in a fully-parallel manner in a synaptic element array having an intersection structure. Accordingly, it is possible to shorten a time for weight update.

Abstract: A method of controlling a resistive memory device includes: accessing a first pulse power specification satisfying a memory cell coefficient associated with at least a first of a plurality of memory cells included in a memory cell array; generating a first pulse power according to the accessed first pulse power specification; and performing a write operation on at least the first of the plurality of memory cells using the generated first pulse power.

Abstract: A resistive memory device includes: a first electrode; a variable resistive material layer that is formed on the first electrode and includes a metal oxide NxMOy (wherein 0.001<x<0.30 and 0.5<y<2.5) doped with nitrogen; and a second electrode that is formed on the variable resistive material layer. The variable resistive material layer has a multibit memory characteristic.

Abstract: A method of controlling a resistive memory device includes: accessing a first pulse power specification satisfying a memory cell coefficient associated with at least a first of a plurality of memory cells included in a memory cell array; generating a first pulse power according to the accessed first pulse power specification; and performing a write operation on at least the first of the plurality of memory cells using the generated first pulse power.

Abstract: Disclosed are a resistance-variable memory device including a carbide-based solid electrolyte membrane that has stable memory at a high temperature and a manufacturing method thereof. The resistance-variable memory device includes: a lower electrode, the carbide-based solid electrolyte membrane arranged on the lower electrode, and an upper electrode arranged on the solid electrolyte membrane. In addition, the method for manufacturing the resistance-variable memory device comprises: a step for forming the lower electrode on a substrate, a step for forming the carbide-based solid electrolyte membrane on the lower electrode, and a step for forming the upper electrode on the solid electrolyte membrane.

Abstract: A three-terminal synapse device may include a drain layer formed on a substrate, a gate layer formed on the drain layer, a source layer vertically stacked on the substrate and facing the drain layer and the gate layer. First and second vertical insulating layers may be formed between the source layer and a stack including the drain layer and the gate layer. The first and second vertical insulating layers have different ion mobilities from each other. The first and second vertical insulating layers may cover side surfaces of the drain layer and the gate layer. The ion mobility of the second vertical insulating layer may be greater than that of the first vertical insulating layer.

Abstract: A resistive random access memory (ReRAM) includes a first electrode, a threshold switching layer formed over the first electrode and configured to perform a switching operation according to an applied voltage, a resistance change layer formed over the threshold switching layer, and configured to perform a resistance change operation, and a second electrode formed over the resistance change layer, wherein the threshold switching layer comprises a stoichiometric transition oxide while the resistance change layer comprises a non-stoichiometric transition metal oxide.

Abstract: A resistive random access memory (ReRAM) includes a first electrode, a threshold switching layer formed over the first electrode and configured to perform a switching operation according to an applied voltage, a resistance change layer formed over the threshold switching layer, and configured to perform a resistance change operation, and a second electrode formed over the resistance change layer, wherein the threshold switching layer comprises a stoichiometric transition oxide while the resistance change layer comprises a non-stoichiometric transition metal oxide.

Abstract: A resistive random access memory (ReRAM) includes a first electrode, a threshold switching layer formed over the first electrode and configured to perform a switching operation according to an applied voltage, a resistance change layer formed over the threshold switching layer, and configured to perform a resistance change operation, and a second electrode formed over the resistance change layer, wherein the threshold switching layer comprises a stoichiometric transition oxide while the resistance change layer comprises a non-stoichiometric transition metal oxide.

Abstract: A resistive random access memory (ReRAM) includes a first electrode, a threshold switching layer formed over the first electrode and configured to perform a switching operation according to an applied voltage, a resistance change layer formed over the threshold switching layer, and configured to perform a resistance change operation, and a second electrode formed over the resistance change layer, wherein the threshold switching layer comprises a stoichiometric transition oxide while the resistance change layer comprises a non-stoichiometric transition metal oxide.