Patents by Inventor I-Hsuan Peng

I-Hsuan Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10424563
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor package. The semiconductor package includes a semiconductor die. A redistribution layer (RDL) structure is disposed on the semiconductor die and is electrically connected to the semiconductor die. An active or passive element is disposed between the semiconductor die and the RDL structure. A molding compound surrounds the semiconductor die and the active or passive element.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: September 24, 2019
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao
  • Patent number: 10410969
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package overlying a portion of the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure, a first semiconductor die and a molding compound. The first semiconductor die is disposed on a first surface of the first RDL structure and electrically coupled to the first RDL structure. The molding compound is positioned overlying the first semiconductor die and the first surface of the first RDL structure. The second semiconductor package includes a first memory die and a second memory die vertically stacked on the first memory die. The second memory die is electrically coupled to first memory die by through silicon via (TSV) interconnects formed passing through the second memory die.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 10, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Chia-Cheng Chang, I-Hsuan Peng
  • Publication number: 20190252351
    Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die and a first molding compound that surrounds the first semiconductor die are disposed on the first surface of the first RDL structure. An IMD structure having a conductive layer with an antenna pattern or a conductive shielding layer is disposed on the first molding compound and the first semiconductor die.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 15, 2019
    Applicant: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Ching-Wen Hsiao, Wei-Che Huang
  • Publication number: 20190131233
    Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.
    Type: Application
    Filed: December 26, 2018
    Publication date: May 2, 2019
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Che-Hung KUO, Che-Ya CHOU, Wei-Che HUANG
  • Publication number: 20190115269
    Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 18, 2019
    Inventors: Chi-Wen Pan, I-Hsuan Peng, Sheng-Liang Kuo, Yi-Jou Lin, Tai-Yu Chen
  • Patent number: 10256210
    Abstract: A semiconductor package structure has a first electronic component on an insulating layer, a dielectric layer on the insulating layer and surrounding the first electronic component, a second electronic component stacked on the first electronic component, wherein an active surface of the first electronic component faces an active surface of the second electronic component, a molding compound on the first electronic component and surrounding the second electronic component, a third electronic component stacked on the second electronic component and the molding compound.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: April 9, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • Patent number: 10217723
    Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: February 26, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang
  • Patent number: 10217724
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: February 26, 2019
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao
  • Publication number: 20190043771
    Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.
    Type: Application
    Filed: June 7, 2018
    Publication date: February 7, 2019
    Inventors: Chia-Cheng CHANG, Tzu-Hung LIN, I-Hsuan PENG, Nai-Wei LIU
  • Publication number: 20190043848
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor die and a first memory die disposed on a first surface of a substrate, wherein the first memory die comprises a first edge facing the semiconductor die. The semiconductor die includes a peripheral region having a second edge facing the first edge of the first memory die and a third edge opposite to the second edge. The semiconductor die also includes a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.
    Type: Application
    Filed: July 24, 2018
    Publication date: February 7, 2019
    Inventors: Chia-Cheng CHANG, I-Hsuan PENG, Tzu-Hung LIN
  • Patent number: 10199318
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 5, 2019
    Assignee: MEDIATEK INC.
    Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Che-Hung Kuo, Che-Ya Chou, Wei-Che Huang
  • Patent number: 10177125
    Abstract: In one implementation, a semiconductor package assembly includes a first semiconductor package having a first semiconductor die and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: January 8, 2019
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao
  • Publication number: 20180323127
    Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 8, 2018
    Applicant: MediaTek Inc.
    Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao, Wei-Che Huang
  • Publication number: 20180269164
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a wiring structure. The semiconductor package structure also includes a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The semiconductor package structure further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The first semiconductor die and the second semiconductor die are separated by a molding material. In addition, the semiconductor package structure includes a first hole and a second hole formed on the second surface of the substrate.
    Type: Application
    Filed: February 27, 2018
    Publication date: September 20, 2018
    Inventors: Tzu-Hung LIN, Chia-Cheng CHANG, I-Hsuan PENG, Nai-Wei LIU
  • Patent number: 10079192
    Abstract: A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 18, 2018
    Assignee: MediaTek Inc.
    Inventors: Ching-Wen Hsiao, Tzu-Hung Lin, I-Hsuan Peng, Tung-Hsien Hsieh, Sheng-Ming Chang
  • Publication number: 20180233452
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package overlying a portion of the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure, a first semiconductor die and a molding compound. The first semiconductor die is disposed on a first surface of the first RDL structure and electrically coupled to the first RDL structure. The molding compound is positioned overlying the first semiconductor die and the first surface of the first RDL structure. The second semiconductor package includes a first memory die and a second memory die vertically stacked on the first memory die. The second memory die is electrically coupled to first memory die by through silicon via (TSV) interconnects formed passing through the second memory die.
    Type: Application
    Filed: February 8, 2018
    Publication date: August 16, 2018
    Inventors: Tzu-Hung LIN, Chia-Cheng CHANG, I-Hsuan PENG
  • Patent number: 10032756
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die and includes a first conductive trace. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die and includes a second conductive trace. The first conductive trace is in direct contact with the second conductive trace.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 24, 2018
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • Patent number: 9997498
    Abstract: In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor die, a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure, and a passive device, embedded in the redistribution layer (RDL) structure and coupled to the semiconductor die.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 12, 2018
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • Patent number: 9978729
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on a bottom surface of the first molding compound. The first semiconductor die is coupled to the first RDL structure. A second redistribution layer (RDL) structure is disposed on a top surface of the first molding compound. A passive device is coupled to the second RDL structure.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: May 22, 2018
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng
  • Publication number: 20180102343
    Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.
    Type: Application
    Filed: July 10, 2017
    Publication date: April 12, 2018
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang