Abstract: In embodiments herein, probabilistic and deterministic logic devices include reduced symmetry materials, such as two-dimensional (2D) transition metal dichalcogenide (TMD) materials (e.g., NbSe2 or MoTe2).

Abstract: An optical modulator includes a modulation region, an input port, an output port, and a modulation actuator. The modulation region includes an inhomogeneous arrangement of two or more different materials having different refractive indexes to structure the modulation region to manipulate one or more optical properties of an optical carrier wave in response to a modulation bias. The input port is optically coupled to the modulation region to inject the optical carrier wave into the modulation region. The modulation actuator is disposed proximate to the modulation region and adapted to apply the modulation bias to the modulation region to generate a modulated wave. The modulation bias adjusts at least one of the different refractive indexes of the inhomogeneous arrangement to provide variable control of the one or more optical properties of the optical carrier wave. The output port is optically coupled to the modulation region to receive the modulated wave.

Abstract: Magnetoelectric magnetic tunnel junction (MEMTJ) logic devices comprise a magnetoelectric switching capacitor coupled to a pair of magnetic tunnel junctions (MTJs) by a conductive layer. The logic state of the MEMTJ is represented by the magnetization orientation of the ferromagnetic layer of the magnetoelectric capacitor, which can be switched through the application of an appropriate input voltage to the MEMTJ. The magnetization orientation of the magnetoelectric capacitor ferromagnetic layer is read out by the MTJs. The conductive layer is positioned between the capacitor and the MTJs. The MTJ ferromagnetic free layers are exchange coupled to the ferromagnetic layer of the magnetoelectric capacitor. The potential of an MTJ free layer is based on a supply voltage applied to the reference layer of the MTJ. The MTJ reference layers have a magnetization orientation that is parallel or antiparallel to the magnetization orientations of the ferromagnetic layer of the magnetoelectric capacitor.

Abstract: A multilayer photonic device is described, including an input region configured to receive an input signal, a multilayer stack optically coupled with the input region to receive the input signal, and an output region optically coupled with the multilayer stack to output an output signal. The multilayer stack can include a first metastructured dispersive region disposed in a first patterned layer of the multilayer stack and a second metastructured dispersive region disposed in a second patterned layer of the multilayer stack and optically coupled with the first metastructured dispersive region. The first metastructured dispersive region and the second metastructured dispersive region can together structure the multilayer stack to generate the output signal in response to the input signal.

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.

Abstract: Inverted pillar capacitors that have a U-shaped insulating layer are oriented with the U-shaped opening of the insulating layer opening toward the surface of the substrate on which the inverted pillar capacitors are formed. The bottom electrodes of adjacent inverted pillar capacitors are isolated from each other by the insulating layers of the adjacent electrodes and the top electrode that fills the volume between the electrodes. By avoiding the need to isolate adjacent bottom electrodes by an isolation dielectric region, inverted pillar capacitors can provide for a greater capacitor density relative to non-inverted pillar capacitors. The insulating layer in inverted pillar capacitors can comprise a ferroelectric material or an antiferroelectric material. The inverted pillar capacitor can be used in memory circuits (e.g., DRAMs) or non-memory applications.

Abstract: Apparatus (10) for the preparation of aerated drinks, comprising: an aerator stage (20) comprising: a removable aerator bottle (30) defining a chamber (32) for receiving a liquid to be aerated; an aerator bottle interface (40) operative to engage the removable aerator bottle (30) and seal the chamber (32) thereof; a gas inlet line (60) operative to fluidly connect a gas source (50) to the aerator bottle interface (40); and a gas supply mechanism (70) for controlling supply of gas from the gas source (50) to the aerator bottle interface (40) via the gas inlet line (60); an aerated liquid dispenser stage (100) comprising: an aerated liquid dispenser outlet (110); a liquid outlet line (120) operative to fluidly connect the aerator bottle interface (40) to the aerated liquid dispenser outlet (110) to allow aerated liquid to flow from the chamber (32) of the removable aerator bottle (30) to the aerated liquid dispenser outlet (110); and a liquid flow controller (130) for controlling discharge of aerated liquid fro

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.

Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the

Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

Abstract: Polynucleotides and vectors can be used for the expression of a transgene in cells, such as liver cells. The expression of the transgene from the polynucleotides and vectors can be useful in gene therapy. Various methods can be used for expressing the transgene from the polynucleotides and vectors in liver cells.

Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.

Abstract: An optical modulator includes a modulation region, input, output, and sink ports, and a modulation actuator. The modulation region includes an inhomogeneous arrangement of two or more different materials having different refractive indexes. The input port is optically coupled to the modulation region to inject an optical carrier wave into the modulation region. The output port is optically coupled to the modulation region to receive and emit a modulated signal having a high state and a low state. The sink port is optically coupled to the modulation region. The modulation actuator is disposed proximate to the modulation region and adapted to apply a modulation bias to the modulation region that influences the different refractive indexes of the inhomogeneous arrangement to selectively steer a portion of optical power of the optical carrier wave to the sink port when the modulated signal is modulated into the low state.

Abstract: Valleytronic devices comprise a channel layer having ferrovalley properties—band-spin splitting and Berry curvature dependence on the polarization of the channel layer. Certain monochalcogenides possess these ferrovalley properties. Valleytronic devices utilize ferrovalley properties to store and/or carry information. Valleytronic devices can comprise a cross geometry comprising a longitudinal portion and a transverse portion. A spin-polarized charge current injected into the longitudinal portion of the device is converted into a voltage output across the transverse portion via the inverse spin-valley Hall effect whereby charge carriers acquire an anomalous velocity in proportion to the Berry curvature and an applied in-plane electric field resulting from an applied input voltage. Due to the Berry curvature dependency on the material polarization, switching the polarity of the input voltage that switches the channel layer polarization also switches the polarity of the differential output voltage.

Abstract: In an embodiment, schedule layers are generated. Each schedule layer has one or more schedule entries and a precedence value. At least one schedule layer includes schedule entries that are generated in a repetitive fashion according to an epoch. A final schedule is created based on a combination of the schedule layers according to an ordering of the precedence value of respective schedule layers. Creating the final schedule includes identifying a gap in the final schedule; and filling the gap using a schedule entry from a schedule layer of the two or more schedule layers selected according to respective precedence values. A real time interface is employed to visually present the final schedule for display. The real time interface is configured to dynamically transform and render the one or more schedule entries into one or more graphical cells visually distinguished from each other based restrictions, team members, or inputs.

Abstract: A turbocharger including a compressor section having a compressor housing with an air inlet and a compressor air discharge and a compressor wheel in the compressor housing. A turbine section having a turbine housing with an exhaust gas inlet and a turbine exhaust gas outlet and a turbine wheel in the turbine housing, the turbine wheel being drivingly connected to the compressor wheel, the exhaust gas inlet being configured to be connected to an engine exhaust passage and the turbine exhaust gas outlet being configured to be connected to an exhaust system. The compressor housing includes a diffuser with a recess that receives the compressor wheel wherein the recess has a sidewall with an upper edge and the compressor wheel has a base plate with an upper surface that is below the upper edge of the sidewall of the recess in the diffuser.

Abstract: Magnetoelectric spin-orbit logic (MESO) devices comprise a magnetoelectric switch capacitor coupled to a spin-orbit coupling structure. The logic state of the MESO device is represented by the magnetization orientation of the ferromagnet of the magnetoelectric switch capacitor and the spin-orbit coupling structure converts the magnetization orientation of the ferromagnet to an output current. MESO devices in which all or at least some of the constituent layers of the device are perovskite materials can provide advantages such as improved control over the manufacturing of MESO devices and high quality interfaces between MESO layers due to the lattice matching of perovskite materials.

Abstract: Technologies for a transistor with a ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a ferroelectric gate dielectric that is lattice matched to the channel of the transistor. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one transistor memory cell.