Abstract: A memory device including a single transistor having functions of RAM and ROM and methods for operating and manufacturing the same are provided. The memory device includes a single transistor formed on a substrate. The transistor may be a memory transistor having a gate with a nonvolatile memory element, or the nonvolatile memory element is provided between the transistor and the substrate.

Abstract: A 2T-1C FRAM, each cell of which includes two transistors and one ferroelectric capacitor so that the “charging” and “discharging” of the ferroelectric capacitor used in conjunction with the p-n junction of the two transistors performs write/read operations without switching thereby avoiding degradation problems such as fatigue and imprint in the 2T-1C FRAM.

Abstract: A method and apparatus for emission lithography using a patterned emitter wherein, in the apparatus for emission lithography, a pyroelectric emitter or a ferroelectric emitter is patterned using a mask and it is then heated. Upon heating, electrons are not emitted from that part of the emitter covered by the mask, but are emitted from the exposed part of the emitter not covered by the mask so that the shape of the emitter pattern is projected onto the substrate. To prevent dispersion of emitted electron beams, which are desired to be parallel, the electron beams are controlled using a magnet, a direct current magnetic field generator or a deflection system, thereby achieving an exact one-to-one projection or an exact x-to-one projection of the desired pattern etched on the substrate.

Abstract: The present invention relates to a matrix type multiple numeration system ferroelectric random access memory using a leakage current of dielectric, which is non-volatile and with which a multiple numeration system is realized, and a method for manufacturing the same. In the memory according to the present invention, the unit cells formed of the dielectric and ferroelectric capacitors are arranged in a matrix, the lower electrodes are connected to bit lines, and the upper electrodes are connected to word lines. Thus, a transistor for selecting cells is included for each word line and each bit line. Therefore, it is possible to heighten the integration degree, since the memory cells are each formed of only a dielectric and a ferroelectric capacitor, and to improve productivity since manufacturing processes are simple.

Abstract: The present invention relates to a matrix type multiple numeration system ferroelectric random access memory using a leakage current of dielectric, which is non-volatile and with which a multiple numeration system is realized, and a method for manufacturing the same. In the memory according to the present invention, the unit cells formed of the dielectric and ferroelectric capacitors are arranged in a matrix, the lower electrodes are connected to bit lines, and the upper electrodes are connected to word lines. Thus, a transistor for selecting cells is included for each word line and each bit line. Therefore, it is possible to heighten the integration degree, since the memory cells are each formed of only a dielectric and a ferroelectric capacitor, and to improve productivity since manufacturing processes are simple.

Abstract: In a disk apparatus using a ferroelectric thin film coated on the surface of a disk as a recording medium, an electrode layer is formed on a substrate and the ferroelectric thin film is formed on the electrode layer, thereby forming a disk. A head is installed on an arm over the disk. The head has a reflector, and a microtip electrode, for creating or erasing polarization of the ferroelectric thin film. An optical system is provided over the head. The head moves towards or away from the disk depending on recorded information (polarization direction), and the movement is read by the optical system. Therefore, a low-priced disk apparatus, capable of freely recording and reproducing information semipermanently, is realized.

Abstract: A ferroelectric random access memory having a discharge circuit for stably discharging pyroelectric charges generated in a ferroelectric capacitor without affecting write and read operations is provided. In the ferroelectric random access memory having the discharge circuit according to the present invention, the pyroelectric charges between the ferroelectric capacitor and the FET of the memory cell, generated during the write and read operations are automatically discharged through a resistor since the resistor is included as a discharge path between the contact point of the ferroelectric capacitor and the FET of the memory unit cell and the grounding point. Accordingly, the function of turning on and off the discharge path for discharging the pyroelectric charges is not necessary and the polarization turbulence due to the pyroelectric charges is not generated.

Abstract: A non-volatile ferroelectric memory using a leakage current of a dielectric and a multi-numeration system ferroelectric memory are provided. Unit cells are formed of a transistor. A dielectric or a ferroelectric is used as a gate insulating material. A ferroelectric capacitor is deposited on the upper portion of the gate insulating material and the upper electrode of a ferroelectric capacitor is used as a gate. "Writing" is performed by selecting a material in which the leakage current of the ferroelectric has a negligible value and the leakage current of the dielectric (used as the gate insulating material) is sharply increased. Charges induced between the drain and the source, are increased by applying the voltages which have various levels and identical pulse widths (in the case of "deleting" voltages, having identical levels and various pulse widths) making the leakage current of a various current densities flow through the gate insulating material.

Abstract: Polarization loss in ferroelectric capacitors can be prevented by consecutively applying partial switching pulses to an imprinted ferroelectric capacitor, which is able to achieve a certain polarization state and the zero polarization state simultaneously, under the condition of utilizing the bistable polarization states as memory logic. This effects an improvement in both the fatigue properties and life expectancy of ferroelectric capacitors.

Abstract: A ferroelectric read and write memory of a nondestructive write and read (NDWR) method in which charges of a gate insulating layer induced by a ferroelectric capacitor are discharged via a separate path, includes a source and a drain provided in both side of a well; a gate insulating layer provided on the well; a gate electrode provided on the gate insulating layer; a ferroelectric layer provided on the gate electrode, to which corresponding charges are induced in the gate electrode depending on its polar states; an upper electrode provided on the ferroelectric layer; and a charge discharging means electrically connected to the gate electrode for discharging charges induced in the gate insulating layer.