Abstract: A method of making a semiconductor device includes comparing a thickness profile of a surface of a wafer with a reference value using a control unit. The method further includes transmitting a control signal to an adjustable nozzle based on the comparison of the thickness profile and the reference value. The method further includes rotating the adjustable nozzle about a longitudinal axis of the adjustable nozzle in response to the control signal.

Abstract: A battery module according to an embodiment of the present disclosure includes a plurality of battery cells, a module case accommodating the plurality of battery cells therein, a busbar frame assembly slidably inserted into the module case to support the plurality of battery cells, the busbar frame assembly including a plurality of busbars electrically connected to electrode leads of the plurality of battery cells, and a fuse unit connected to at least one pair of busbars of the plurality of busbars, the fuse unit being provided between the at least one pair of busbars.

Abstract: A plasma processing apparatus includes a chamber providing a space for processing a substrate, a substrate stage configured to support the substrate within the chamber and including a lower electrode, an upper electrode facing the lower electrode, a focus ring in or on an upper peripheral region of the substrate stage to surround the substrate, and a plasma adjustment assembly in at least one of a first position between the upper electrode and the lower electrode and a second position between the focus ring and the lower electrode, the plasma adjustment assembly including a photoreactive material layer and a plurality of light sources configured to irradiate light onto a local region of the photoreactive material layer. A capacitance of the local region is changed as the light is irradiated to the local region.

Abstract: According to an embodiment, an electronic device may comprise: a first housing structure comprising a first surface facing in a first direction, a second surface facing in a second direction opposite to the first direction, a first side surface and a second side surface facing opposite to each other and surrounding at least a part of the space between the first surface and the second surface, and a third side surface and a fourth side surface facing opposite to each other while being perpendicular to the first side surface; a second housing structure comprising a third surface facing in a third direction, a fourth surface facing in a fourth direction opposite to the third direction, a fifth side surface and a sixth side surface facing opposite to each other and surrounding at least a part of the space between the third surface and the fourth surface, and a seventh side surface and an eighth side surface facing opposite to each other while being perpendicular to the fifth side surface; a hinge structure connec

Abstract: A display apparatus includes a panel driver; a display panel including a plurality of pixels connected to a plurality of gate lines and a plurality of data lines through a plurality of switching elements; and a processor configured to control the panel driver to output a gate signal through the plurality of gate lines, and display an image in the display panel by controlling the panel driver to apply, through the plurality of data lines, data voltage to pixels, from among the plurality of pixels, connected with switching elements, from among the plurality of switching elements, to which the gate signal is output, wherein the processor is further configured to control, based on a user input for selecting a ratio of the image, the panel driver to output the gate signal to at least one first gate line connected with a first subset of pixels, from among the plurality of pixels, for displaying the image according to the user input.

Abstract: An overlay mark, an overlay measurement method using the same, and a manufacturing method of a semiconductor device using the same are provided. The overlay mark is for measuring an overlay based on an image, is configured to determine a relative misalignment between at least two pattern layers, and includes first to fourth overlay marks. The first overlay mark has a pair of first Moire patterns disposed on a center portion of the overlay mark. The second overlay mark has a pair of second Moire patterns disposed so as to face each other with the first Moire patterns interposed therebetween. The third overlay mark has a pair of third Moire patterns disposed on a first diagonal line with the first Moire patterns interposed therebetween. The fourth overlay mark has a pair of fourth Moire patterns disposed on a second diagonal line with the first Moire patterns interposed therebetween.

Abstract: A memory device and an operating method of the memory device are provided. The operating method comprises receiving an activation-refresh command from a memory controller, decoding a target address and an internal command from the activation-refresh command, and performing an activation operation based on the internal command for the target address and performing a refresh operation on at least one block to which the target address does not belong.

Abstract: Redistribution layers of integrated circuits include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.

Abstract: A memory device includes a memory cell array connected to a plurality of wordlines and a plurality of bitlines; a row decoder configured to select a wordline, among the plurality of wordlines, in response to a row address; a column decoder configured to corresponding bitlines, among the plurality of bitlines, in response to a column address; a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines; a row hammer detector configured to generate a refresh row address when the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; and a refresh controller configured to perform a refresh operation on a row corresponding to the refresh row address. The row corresponding to the refresh row address is disposed adjacent to the row corresponding to the row address.

Abstract: The present disclosure relates to a display apparatus using a semiconductor light-emitting device, the display apparatus comprising: a base substrate; a row driver which provides 3-state first signals including a high, a ground, and a low signal; a column driver which provides 2-state second signals including a high and a low signal; and a plurality of semiconductor light-emitting devices provided on the base substrate, wherein the plurality of semiconductor light-emitting devices include a first semiconductor light-emitting device and a second semiconductor light-emitting device which are connected to the row driver and the column driver in different pole directions.

Abstract: A non-volatile memory and a programming method thereof are provided. The programming method of the non-volatile memory includes the following steps. A coarse programming procedure is performed for programing all of a plurality of memory cells at an erase state to 2{circumflex over (?)}N?1 or 2{circumflex over (?)}N program states. N is a positive integer. A fine programming procedure is performed for pushing all of memory cells into 2{circumflex over (?)}N?1 or 2{circumflex over (?)}N verify levels.

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

Abstract: A system and method of determining an allergy impact profile of an individual are disclosed. The system and method may be employed to predict allergy impact environmental conditions may have on allergy symptoms of an individual and to recommend treatment of the individual in response to the predicted allergy impact.

Abstract: An image sensor includes a substrate having a pixel area in which a plurality of active areas is defined. A first transistor includes a first gate electrode including a buried gate portion. The buried gate portion is buried in the substrate in a first active area selected from the plurality of active areas. A second transistor includes a second gate electrode overlapping the buried gate portion on the first active area in a vertical direction.

Abstract: Provided are a system and a method for prediction of an intradialytic adverse event, where a machine learning model of two-class classification is utilized to predict intradialytic adverse events in quasi-real time, such that features extracted in an ongoing hemodialysis process in real time can have the hemodialysis session alerted for forthcoming adverse events. Therefore, clinicians can be warned to take necessary actions and adjust the hemodialysis machine settings in advance. In addition, a computer readable medium thereof is also provided.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate and an active pattern formed over the substrate and including first to fourth regions. A gate insulation layer is formed over the active pattern and the substrate, and a first gate electrode is formed over the gate insulation layer and partially overlapping the active pattern. The first gate electrode, the first region and the second region define a first transistor. A second gate electrode is formed on the same layer as the first gate electrode. The second gate electrode, the third region and the fourth region define a second transistor, and the second gate electrode, the second region and the fourth region define a third transistor. A first insulating interlayer is formed over the first gate electrode, the second gate electrode, and the gate insulation layer.

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

Abstract: A semiconductor device includes nanosheets between the source/drain regions, and a gate structure over the substrate and between the source/drain regions, the gate structure including a gate dielectric material around each of the nanosheets, a work function material around the gate dielectric material, a first capping material around the work function material, a second capping material around the first capping material, wherein the second capping material is thicker at a first location between the nanosheets than at a second location along a sidewall of the nanosheets, and a gate fill material over the second capping material.

Abstract: Disclosed is an image sensor comprising a substrate that includes a plurality of pixel groups each including a plurality of pixel regions, a plurality of color filters two-dimensionally arranged on a first surface of the substrate, and a pixel separation structure in the substrate. The pixel separation structure includes a first part that defines each of the pixel regions and a second part connected to the first part. The second part runs across an inside of each of the pixel regions.

Abstract: An alert management and real-time remediation system is disclosed. The system may receive, from an institution, an electronic file that includes an exception information (EI) data structure comprising exception information representing events and customers associated with the events, and a contact information data structure comprising an electronic address for each customer. The system may automatically parse the EI into events associated with the customers, and for each customer, send an event notification message (EN) to the electronic address of the customer, wherein the event notification message includes a link to an authentication interface of the institution associated with the customer.