Abstract: Disclosed herein are a point cloud data transmission method including encoding point cloud data, and transmitting point cloud data, and a point cloud data reception method including receiving point cloud data, decoding the point cloud data, and rendering the point cloud data.

Abstract: A lithium ion secondary battery according to the present disclosure includes: an electrode assembly; and a case having a structure in which upper stamped portions and lower stamped portions are repeatedly stamped to cover the outside of the electrode assembly, and the upper stamped portions and the lower stamped portions form a corrugated pattern, and the electrode assembly includes: one or more unit cells each equipped with a pair of electrodes having different polarities with a separator interposed therebetween; an electrode mixture coated on one or both surfaces of the pair of electrodes; and electrode tabs protruded from the respective electrodes and not coated with the electrode mixture, and the electrode tabs include an electrode parallel connection tab and an electrode lead connection tab, and any one or more of the electrode parallel connection tab and the electrode lead connection tab is formed on the electrodes, and the corrugated pattern has various intervals.

Abstract: Various embodiments of an electronic device for matching an antenna impedance may include an antenna, a wireless communication module, an impedance matching module, and at least one processor, wherein the at least one processor is configured to: select a first index corresponding to an impedance of the antenna among a plurality of sampled indexes through a first measurement in which a tuning code of the impedance matching module is configured as a reference code; identify a use environment corresponding to the first index; select a second index corresponding to the impedance of the antenna among the plurality of sampled indexes through a second measurement in which the tuning code of the impedance matching module is configured as the reference code and as a ground code corresponding to the use environment; and adjust the impedance of the antenna based on a tuning code corresponding to the second index.

Abstract: A method of producing a positive electrode material for a secondary battery includes preparing a lithium composite transition metal oxide containing nickel, cobalt, and manganese, forming a coating layer on a surface of the lithium composite transition metal oxide, and post-treating the lithium composite transition metal oxide having the coating layer formed thereon, wherein the post-treating is performed by exposing the lithium composite transition metal oxide having the coating layer formed thereon to moisture at a relative humidity of 10% to 50% at 25° C., and then heat treating the lithium composite transition metal oxide to remove residual moisture.

Abstract: A non-aqueous electrolyte solution for a lithium secondary battery and a lithium secondary battery including the same. Specifically, the non-aqueous electrolyte solution for a lithium secondary battery of the present disclosure may include a lithium salt; a non-aqueous organic solvent; and an oligomer including a repeating unit derived from a monomer represented by Formula 1, a repeating unit derived from a monomer represented by Formula 2, and a repeating unit derived from a monomer represented by Formula 3. Also, the lithium secondary battery of the present disclosure may improve cycle characteristics and high-temperature storage characteristics by including the above non-aqueous electrolyte solution for a lithium secondary battery.

Abstract: A multilayer ceramic electronic component includes: a ceramic body including a dielectric layer having a main component represented by (Ba1-xCax) (Ti1-y(Zr, Hf)y)O3 (where, 0?x?1, 0?y?0.5), and including first and second internal electrodes alternately stacked with the dielectric layer interposed therebetween; a first external electrode connected to the first internal electrode; and a second external electrode connected to the second internal electrode, wherein at least one of the dielectric layer and the internal electrode includes Sn or Dy. If Sn, an average content of Sn at an interface between the dielectric layer and the internal electrode is within a range of 5 at % or more and 20 at % or less. If Dy, an average content of Dy at an interface between the dielectric layer and the internal electrode is within a range of 1 at % or more and 5 at % or less.

Abstract: According to an embodiment of the present disclosure, a method for performing SL communication by a first device is provided. The method comprises the steps of: determining a plurality of first bits on which interleaving is to be performed from among a plurality of bits of a first encoded code block and a plurality of second bits except for the plurality of first bits from among the plurality of bits of the first encoded code block; performing interleaving on the plurality of first bits; transmitting, to a second device, the plurality of first bits on which the interleaving has been performed, on a plurality of first REs related to the plurality of first bits; and transmitting, to the second device, the plurality of second bits on a plurality of second REs related to the plurality of second bits.

Abstract: A display panel includes a first display substrate including first to third pixel areas and a light blocking area that is adjacent to the first to third pixel areas and a second display substrate including first to third display elements respectively overlapping the first to third pixel areas. The first display substrate includes a base substrate, a first color filter overlapping the first pixel area and having a first color, a second color filter overlapping the second pixel area and having a second color different from the first color, a third color filter disposed on the base substrate, having a third color different from the first and second colors, and including a filter portion overlapping the third pixel area and a light blocking portion overlapping the light blocking area, and a light blocking member disposed on the light blocking portion and containing a black organic pigment.

Abstract: Proposed is a method of performing wireless communication by a first apparatus. The method may include receiving one or more reference signals, each generated by one or more apparatuses, from the one or more apparatuses, and determining discontinuous detection (DTX) related to one or more second apparatuses among the one or more apparatuses based on the one or more reference signals, and transmitting hybrid automatic repeat request (HARD) feedback to the one or more second apparatuses.

Abstract: Disclosed are a non-volatile memory device, a memory system including the same and a read method of the memory system, in which the non-volatile memory device includes a first storage in which a basic offset level for a read retry operation is stored, a second storage in which an additional offset level for the read retry operation is stored, and a voltage generator suitable for adjusting, when the read retry operation is performed, a read voltage by using the basic offset level and further by selectively using the additional offset level depending on a read operation.

Abstract: A circuit board mounting support for supporting a first electronic circuit integration includes a bearing member. The first electronic circuit integration includes a circuit board, an electronic component engaged with a first surface of the circuit board, and multiple legs for engaging with the bearing member. The circuit board has a mounting area for mounting the electronic component and a second surface opposite to the first surface. The bearing member includes a groove and an engaging portion connected to a peripheral edge of the groove. A corresponding area is defined on the bearing member and corresponds to the mounting area of the circuit board. When the bearing member is engaged with the circuit board, an opening of the groove and the engaging portion face the second surface. A junction that each of the legs is engaged with the bearing member is located out of the corresponding area.

Abstract: An operation method of a nonvolatile memory device includes performing a 1-stage program step and a 1-stage verify step on a first word line, storing a first time stamp, performing the 1-stage program step and the 1-stage verify step on a second word line, storing a second time stamp, calculating a delay time based on the first time stamp and the second time stamp, determining whether the delay time is greater than a threshold value, adjusting at least one 2-stage verify voltage associated with the first word line from a first voltage level to a second voltage level based on the delay time, and performing a 2-stage program step and a 2-stage verify step on the first word line. A level of the at least one 1-stage verify voltage is lower than the second voltage level, and the second voltage level is lower than the first voltage level.

Abstract: A semiconductor device includes a fin structure protruding from a first isolation insulating layer provided over a substrate, a gate dielectric layer disposed over a channel region of the fin structure, a gate electrode layer disposed over the gate dielectric layer, a base semiconductor epitaxial layer disposed over a source/drain region of the fin structure, and a cap semiconductor epitaxial layer disposed over the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer, and a surface roughness of the cap semiconductor epitaxial layer along a source-to-drain direction is greater than zero and smaller than a surface roughness of the base semiconductor epitaxial layer along the source-to-drain direction.

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Abstract: Semiconductor devices may include a substrate, an active region that is on the substrate and extends in a first direction, a gate structure that traverses the active region and extends in a second direction that may be different from the first direction, a source/drain region on the active region adjacent a side of the gate structure, an insulating layer on the substrate, the gate structure and the source/drain region, and a contact structure that is in the insulating layer and is connected to the source/drain region. In the source/drain region, a contact region that is in contact with the contact structure includes first and second side regions spaced apart from each other in the second direction and a central region between the first and second side regions, and at least one of the first and second side regions may include a recess.

Abstract: Methods, systems, and devices for die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.

Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

Abstract: A highly integrated multi-channel optical module is provided. The optical module includes an optical source device mounted on a substrate by an optical source mount unit, a waveguide mounted on the substrate by a waveguide mount unit, a lens mount unit disposed between the optical source device and the waveguide and mounted on the substrate, and a lens unit fixed to the lens mount unit by an adhesive cured by ultraviolet (UV) parallel light, wherein a light path of the UV parallel light is formed in the lens mount unit by a reflector attached on a side surface of the lens mount unit, and the UV parallel light moves along the light path and cures the adhesive coated on an upper portion of the lens mount unit facing a lower end portion of the lens unit.

Abstract: A vertical channel thin film transistor includes substrate, lower source/drain electrode, spacer layer, upper source/drain electrode covering portion of upper surface of the spacer layer, interlayer insulating pattern covering portion of upper surface of the upper source/drain electrode and upper surface of the spacer layer exposed by the upper source/drain electrode, contact hole disposed on the lower source/drain electrode and passing through the interlayer insulating pattern, the upper source/drain electrode, and the spacer layer, active pattern covering inner wall and bottom surface of the contact hole and extending over upper surface of the upper source/drain electrode and upper surface of the interlayer insulating pattern, gate insulating pattern filling portion of the contact hole and extending along upper surface of the active pattern, and gate electrode filling portion of the contact hole and extending along upper surface of the gate insulating pattern.

Abstract: A multilayer ceramic electronic component includes: a ceramic body and first and second external electrodes on external surfaces of the ceramic body. The ceramic body includes first and second internal electrodes facing each other with dielectric layers interposed therebetween. The ceramic body includes an active portion in which capacitance is formed and cover portions on upper and lower surfaces of the active portion, respectively. The ratio of the thickness of the first and second external electrodes to the thickness of the cover portion is proportional to the inverse of the cube root of the ratio of the Young's Modulus of each of the first and second external electrodes to the Young's modulus of the cover portion.