Abstract: A display apparatus is disclosed that includes a substrate including a pixel circuit area and a driving circuit region, a sub-gate driving circuit disposed over the pixel circuit area, a main gate driving circuit arranged on a left side or a right side of the pixel circuit area, a main gate signal output line configured to transfer an output signal of the main gate driving circuit, a sub-gate signal output line configured to transfer an output signal of the sub-gate driving circuit, and a plurality of input lines crossing the main gate signal output line, wherein the plurality of input lines extend to cross the sub-gate signal output line.

Abstract: A training method of a memory device adjusting an eye window of a data signal in response to a duty cycle adjuster (DCA) includes performing a first training operation that selects a first DCA code corresponding to a first internal clock signal having a phase difference of 180° relative to a reference internal clock signal, and performing a second training operation that selects a second DCA code and a third DCA code respectively corresponding to a second internal clock signal and a third internal clock signal having a phase difference of 90° and 270° relative to reference internal clock signal. In the first training operation, the eye window size of the data signal is measured in units of two unit intervals, and in the second training operation, the eye window size of the data signal is measured in units of one unit interval.

Abstract: A display apparatus for reducing a reduction in image quality due to signal interference between adjacent lines comprises a substrate, pixels comprising at least a first pixel group to a third pixel group, data lines comprising at least a first data line to a third data line, and a data distributor for alternately transferring data signals to at least one pair of data lines among the data lines, wherein one end of a first horizontal line of the first data line is arranged adjacent to blue-based pixels of the first pixel group, one end of a second horizontal line of the second data line is arranged adjacent to green-based pixels of the second pixel group, and one end of a third horizontal line of the third data line is arranged adjacent to blue-based pixels of the third pixel group.

Abstract: A method of compensating a display device includes: displaying a first display image of a calibration pattern; generating a first photograph image of the calibration pattern by capturing the first display image; generating a measurement representative position data corresponding to the calibration pattern by measuring the first photograph image; generating a third-order fitting representative position data by performing a two-dimensional third-order fitting; displaying a second display image of a full white display; generating a second photograph image of the full white display by capturing the second display image; generating a first crop image by performing a size adjustment based on the third-order fitting representative position data; calculating a luminance compensation value by comparing a measured luminance of the first crop image with a target luminance; and generating a compensated image data by applying the luminance compensation value to an image data.

Abstract: A display apparatus includes pixels, each of the pixels including a light-emitting diode, a first transistor connected to a driving voltage line and the light-emitting diode, a second transistor connected to the first transistor and the light-emitting diode, a third transistor connected to the second transistor and a first initialization voltage line, and a fourth transistor connected to the light-emitting diode and a second initialization voltage line. During a frame, each of the pixels operates in a first scan period and a second scan period. The first scan period includes a write-period in which a data signal is supplied and a first emission period in which the pixel is configured to emit light at a brightness corresponding to the data signal.

Abstract: A magnetic coupling device according to an embodiment of the present invention includes a first bobbin including an upper surface, a lower surface, and an outer surface, a groove portion which is disposed on the inner side of the outer surface and is concave from the upper surface toward the lower surface, and a first terminal portion and a second terminal portion which are disposed on the outer surface and spaced apart from each other; a second bobbin disposed on the groove portion and accommodating a magnetic substance core; and a first coil and a second coil which are wound on the second bobbin and spaced apart from each other, wherein the first coil includes a first winding portion and a first extension portion, and the second coil includes a second winding portion, and a second extension portion.

Abstract: A magnetic tunneling junction device includes a synthetic antiferromagnet, a separation metal layer disposed on the synthetic antiferromagnet, a free layer disposed on the separation metal layer and having a variable magnetization direction, an oxide layer disposed on the free layer, and a pinned layer disposed on the oxide layer and having a pinned magnetization direction. The synthetic antiferromagnet may include a first ferromagnetic layer, a non-magnetic metal layer disposed on the first ferromagnetic layer, and a second ferromagnetic layer disposed on the non-magnetic metal layer. Magnetization directions of the first ferromagnetic layer and the second ferromagnetic layer may be opposite to each other in an in-plane direction and aligned to be inclined with respect to a direction of a current applied to the synthetic antiferromagnet.

Abstract: A multi-stack semiconductor device includes a substrate, a device isolation layer, first channels, first gate lines covering the first channel, extending in a second horizontal direction, and spaced apart from each other in the first horizontal direction, first source/drain areas arranged on both sides of each of the first channels in the first horizontal direction, a second channel arranged apart from the first gate line in the vertical direction over any one of the first gate lines, a second gate line, second source/drain areas, a third channel arranged apart from the second gate line in the vertical direction over the second gate line, a third gate line, third source/drain areas, and a first lower source/drain contact extending in the vertical direction and connected to each of the first source/drain area, the second source/drain area, and the third source/drain area.

Abstract: A memory device is provided. The memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns and rows and including first and second memory cells in a same column and different rows, the plurality of columns intersecting the plurality of rows in a plan view, a first bit line transistor electrically connected between the first memory cell and a first bit line metal line and a second bit line transistor electrically connected between the second memory cell and a second bit line metal line, wherein the first bit line metal line is on an upper surface of the memory cell array, and the second bit line metal line is on a lower surface of the memory cell array opposite the upper surface of the memory cell array.

Abstract: An integrated circuit device includes a substrate including a plurality of active regions that include a first active region and a second active region that is adjacent to the first active region, a bit line that extends on the substrate in a horizontal direction, a first direct contact connected to the first active region, a second direct contact between the first direct contact and the bit line, an inner nitride film connected to a sidewall of the first direct contact and a sidewall of the second direct contact, an isolation film between the first active region and the second active region, and an outer oxide film that is connected to at least one surface of the second active region and between the inner nitride film and the second active region.

Abstract: A method for producing a cable by covering with polytetrafluoroethylene and extrusion molding with a perfluoroalkoxy compound, including: covering an outer surface of a conductor with an insulation layer; and extrusion molding a skin layer on an outer surface of the insulation layer to form a cable. The insulation layer and the skin layer are made of polytetrafluoroethylene and a perfluoroalkoxy compound, respectively. The perfluoroalkoxy compound and polytetrafluoroethylene both have high temperature resistance, good electronic signal transmitting performance, and non-bonding surface, etc., and the perfluoroalkoxy compound has a Shore hardness of 60 to 70D, which can impart the skin layer a certain hardness, and is suitable for being extrusion molded on the outer surface of the insulation layer made of polytetrafluoroethylene, so as to support the insulation layer and prevent the insulation layer from being deformed. Therefore, the perfluoroalkoxy compound is the most suitable material for the skin layer.

Abstract: A semiconductor device includes a substrate, a word line extending on the substrate in a first horizontal direction, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, and a spacer structure on one sidewall of the bit line, wherein the bit line includes a lower conductive layer, an intermediate conductive layer, and an upper conductive layer stacked in a vertical direction on the substrate, and the spacer structure includes a depletion stopping layer on one sidewall of the lower conductive layer, extending in the vertical direction and including a material layer having an interfacial trap density less than an interfacial trap density of a silicon nitride layer, and an inner spacer extending in the vertical direction and on one sidewall of the depletion stopping layer.

Abstract: An integrated circuit device includes a substrate having a main surface and fin-type active regions protruding in a vertical direction from the main surface and extending lengthwise in a first horizontal direction, gate lines extending parallel to one another in a second horizontal direction perpendicular to the first horizontal direction and crossing the fin-type active regions, source/drain regions on the fin-type active regions between the gate lines, an inter-gate insulation layer covering the source/drain regions between the gate lines, active contacts on and in contact with the source/drain regions, and a buried insulation block between adjacent ones of the source/drain regions in the second horizontal direction, the buried insulation block penetrating through at least a portion of the inter-gate insulation layer and having a top surface in contact with a first active contact of the active contacts.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in an NMOS region, a second source/drain epitaxial feature disposed in the NMOS region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a third source/drain epitaxial feature disposed in a PMOS region, a second dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature, and a conductive feature disposed over the first, second, and third source/drain epitaxial features and the first and second dielectric features.

Abstract: A microelectronic device includes a GaN FET on a substrate such as silicon and a buffer layer of a GaN semiconductor material. The GaN FET includes a contact etch stop and a stretch contact electrically connecting a source region with the contact etch stop. The contact etch stop may stretch over a p-type GaN gate structure towards a drain region to form a field plate connected to the source region. The contact etch stop provides a method to connect the field plate to the source region which allows efficient area scaling of space between the source region and the p-GaN gate structure. Disclosed examples provide an associated process flow for forming such GaN FETs.

Abstract: An integrated circuit device includes a fin-type active region on a substrate, a nanosheet on a fin top surface of the fin-type active region, the nanosheet being apart from the fin top surface of the fin-type active region in a vertical direction, a gate line surrounding the nanosheet on the fin-type active region, and a source/drain region on the fin-type active region, the source/drain region being in contact with the nanosheet, wherein the nanosheet includes a multilayered sheet comprising a first outer semiconductor sheet, a core semiconductor sheet, and a second outer semiconductor sheet, which are sequentially stacked in the vertical direction.

Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor stack on a semiconductor substrate in a flat state, the semiconductor stack including sacrificial layer portions and channel layer portions that are alternately stacked over one another; forming source/drain trenches in the semiconductor stack, each of the source/drain trenches penetrating the channel layer portions, the sacrificial layer portions and an upper portion of the semiconductor substrate, and terminating at a lower portion of the semiconductor substrate, so as to form the channel layer portions into channel features and form the sacrificial layer portions into sacrificial features; transforming the semiconductor substrate from the flat state to a bending state; forming source/drain regions in the source/drain trenches, respectively; and reverting the semiconductor substrate from the bending state back to the flat state, so as to induce a strain in the channel features.

Abstract: The present invention relates to a thyristor having a vertical structure and a cross-point memory array including the same. The thyristor having a vertical structure according to one embodiment may include a semiconductor core with an insulating film formed on the outer peripheral surface thereof, and a plurality of metal layers formed on the insulating film. In the semiconductor core, at least one layer of a base layer and an emitter layer may be formed on a region corresponding to each of the metal layers based on the charge plasma phenomenon due to the difference in work function with the metal layers.

Abstract: The present invention relates to a transistor based on a compact drain and hetero-material structure. The transistor according to one embodiment includes substrates including a buried oxide (BOX) layer and active layers formed on the buried oxide layer; an insulating layer formed on the substrates; and electrode layers formed on the insulating layer and including a drain electrode, a gate electrode, and a source electrode. The active layers include a first semiconductor layer corresponding to a drain region, a second semiconductor layer corresponding to a channel region, and a third semiconductor layer corresponding to a source region. The first semiconductor layer is formed to be thinner than the second semiconductor layer, and the third semiconductor layer is formed of a material having a band gap lower than that of the second semiconductor layer.