Abstract: A display device may include pixel areas each including a first area and a second area; and a pixel in each pixel area. The pixel may include first to fifth insulating layers stacked on a substrate; a power line on the substrate; a pixel circuit component provided in the first area, and including a transistor disposed on the substrate and electrically connected to the power line; and an emission component provided in the second area, and including first, second, and third alignment electrodes disposed on the substrate, and a light emitting element disposed between the first, second, and third alignment electrodes. At least one of the first to the fifth insulating layers may be disposed under the first to the third alignment electrodes and may include an inorganic insulating layer.

Abstract: Disclosed herein is a pouch-type battery case including a pouch film laminate. A cup part can include a bottom surface and a side surface, and a flat part disposed to surround the cup part. The side surface can include a first curved portion, a planar portion, and a second curved portion, the pouch film laminate can include a base material layer, a sealant layer and gas barrier layer disposed therebetween. The pouch-type battery case is configured to satisfy Equation 1: 0.01? D/{A?(RP+RD+C)}, where D is the gas barrier layer thickness, A is a vertical depth of the cup part, RP is a curvature radius of the first curved portion between the bottom surface and the flat part, RD is a curvature radius of the second curved portion between the planar portion and the flat part, and C is a horizontal length of the planar portion.

Abstract: An image sensor may include a pixel isolation structure disposed in a semiconductor substrate to define a first pixel region, first and second photoelectric conversion regions disposed in the first pixel region, and a separation structure disposed in the first pixel region, between the first and second photoelectric conversion regions. The pixel isolation structure may include first pixel isolation portions, which are spaced apart from each other in a second direction and extend lengthwise in a first direction, and second pixel isolation portions, which are spaced apart from each other in the first direction and extend lengthwise in the second direction to connect to the first pixel isolation portions. The separation structure may be spaced apart from the pixel isolation structure in the first direction and the second direction, and is at least partly at the same level as the first and second photoelectric conversion regions in a third direction perpendicular to the first direction and the second direction.

Abstract: Disclosed herein is a pouch film having a base material layer, a gas barrier layer, and a sealant layer. The gas barrier layer may include stainless steel and may be disposed between the base material layer and the sealant layer. A difference between a rupture energy measured along a machine direction (MD) of the gas barrier layer and a rupture energy measured along a transverse direction (TD) of the gas barrier layer may be less or equal to 2000 J.

Abstract: A light-emitting device includes a carrier, a reflection layer, a common electrode and a first semiconductor stack. The carrier has a light-emitting region, an electrical connection region and a trench, which separates the light-emitting region from the electrical connection region. The reflection layer is disposed on a sidewall of the trench. The common electrode is disposed in the electrical connection region. The first semiconductor stack is disposed in the light-emitting region, wherein a first type semiconductor layer of the first semiconductor stack is electrically connected to the common electrode. A light-emitting apparatus including the light-emitting device is also provided.

Abstract: A battery module includes a battery cell stack including a plurality of battery cells arranged and stacked in a first direction; a module housing configured to accommodate the battery cell stack; and a deformation prevention structure disposed between the module housing and an outermost peripheral battery cell among the plurality of battery cells, in which the module housing includes a housing plate adjacent to the outermost peripheral battery cell, and in which the deformation prevention structure includes: a pressing plate fixed to the housing plate and supported on the battery cell stack; a flat spring disposed between the pressing plate and the housing plate; and a protruding portion supported on the pressing plate and protruding from an outer surface of the housing plate.

Abstract: Provided are a capacitor and a semiconductor device including the same. The capacitor includes a first electrode, a dielectric layer over the first electrode, a second electrode between the first electrode and the dielectric layer, and a third electrode over the dielectric layer and in contact with the dielectric layer such that the dielectric layer is between the second electrode and the third electrode. A thermal expansion coefficient of the first electrode may be greater than a thermal expansion coefficient of the dielectric layer, and a work function of the second electrode may be higher than a work function of the first electrode.

Abstract: A battery module includes a plurality of battery cells, a cell frame configured to receive the plurality of battery cells, a busbar configured to connect the plurality of battery cells to each other in series and/or in parallel, and a bonding wire configured to electrically connect the battery cells to the busbar. The busbar includes one or more first busbars located at an upper part of the cell frame and two second busbars located at opposite side surfaces of the cell frame. The cell frame and the busbar are integrally formed by insert injection molding.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

Abstract: The present invention relates to a coupler having a spiral coupling line, and may include a coupler body including ground electrodes and port electrodes for power connection to an outside on a lower surface; a first coupling line located inside the coupler body, electrically connected to at least one of the port electrodes, and having a spiral structure as a whole; a second coupling line located inside the coupler body, electrically connected to at least another one of the port electrodes, and having a shape corresponding to the first coupling line; and an internal ground pattern electrically connected to the ground electrodes.

Abstract: A semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. The gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material.

Abstract: An antenna structure includes a metal mechanism element, a first radiation element, a second radiation element, an impedance element, and a dielectric substrate. The metal mechanism element has a slot. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The impedance element is coupled to the metal mechanism element. The impedance element is disposed between the first radiation element and the second radiation element. The dielectric substrate is adjacent to the slot of the metal mechanism element. The first radiation element, the second radiation element, and the impedance element are disposed on the dielectric substrate. The impedance element is configured to increase the isolation between the first radiation element and the second radiation element.

Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.

Abstract: An anode for secondary battery including an anode current collector; a first layer including a binder and contacting at least one cross-section of the anode current collector in a thickness direction; and a second layer including an anode active material and contacting one cross-section of the first layer in a thickness direction. An end portion of the first layer in a width direction perpendicular to the thickness direction protrudes more than an end portion of the second layer in a width direction.

Abstract: A lattice structure includes a first layer and a second layer disposed on and overlaying the first layer. The first layer includes a plurality of interior cells, and adjacent interior cells along both a first axis and a second axis are interconnected. The second layer includes a plurality of exterior cells, and adjacent exterior cells are connected along the second axis but not the first axis. A channel is formed between unconnected adjacent exterior cells above interconnected adjacent interior cells. The lattice structure may be formed during a method of manufacturing a protective pad that further includes folding the lattice structure according to a pattern to form an articulated protective structure.

Abstract: At least some embodiments herein are related to a semiconductor chip assembly comprising: a memory containing information related to entering a standard state for a vanadium-based battery; and a processor, operatively connected with the memory, that provides instructions or commands related to entering the standard state for the vanadium-based battery, by setting a constant temperature that is used in performing open circuit voltage (OCV) measurements, by setting one or more voltage values with respect to a particular voltage region that is used in performing the OCV measurements, and maintaining an equilibrium state of the vanadium-based battery while performing the OCV measurements. Also disclosed is a method comprising: entering a standard state for a vanadium-based battery and maintaining an equilibrium state of the vanadium-based battery while performing the OCV measurements.

Abstract: The present disclosure relates to a diagnostic method and a device performing the same. According to an aspect of the present disclosure, a diagnostic device is a diagnostic device that uses a test kit including a specimen plate having a specimen region in which a specimen is smeared and a patch plate configured to store a contact-type patch, which comes into contact with the specimen to stain the specimen, and the diagnostic device includes a body having a loading region in which the test kit is placed, a moving unit configured to move the patch plate and the specimen plate of the test kit relative to each other so that the specimen placed in the test kit is smeared in the specimen region, and a contact unit configured to move a structure of the test kit such that the contact-type patch comes into contact with the smeared specimen so that the smeared specimen is stained.

Abstract: A solid oxide cell stack includes a first end plate having a flow path, a solid oxide cell disposed on the first end plate, and a second end plate including a lower region disposed on the solid oxide cell and having a first through-hole, and an upper region disposed on the lower region and having a second through-hole. In the second end plate, an inner sidewall of the upper region forming the second through-hole is inclined such that a width of the second through-hole increases in an upward direction.

Abstract: A power amplifier includes: a power transistor to receive a power voltage; a first transistor including a first terminal to provide a bias current to the power transistor; and an overpower protection circuit to generate a first current corresponding to the power voltage and to provide the first current to a second terminal of the first transistor. The overpower protection circuit includes: a limiting current source to provide a limiting current to the second terminal of the first transistor; and a sink current generating circuit including a second transistor that includes a control terminal to which a voltage corresponding to the power voltage is applied and a first terminal connected to the second terminal of the first transistor, and to sink a second current from the limiting current.

Abstract: An electrode assembly includes a plurality of unit cells each equipped with a pair of electrodes having different polarities. Electrode tabs protrude from the electrodes. The electrode tabs including at least one electrode parallel connection tab and at least one electrode lead connection tab. In a first unit cell of the plurality of unit cells, a current collector of a first electrode among the pair of electrodes is made of a different material from a current collector of a second electrode among the pair of electrodes having the different polarity.