Patents by Inventor Ionut Radu

Ionut Radu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180309426
    Abstract: A production method for a surface acoustic wave device comprises the following steps: a step of providing a piezoelectric substrate comprising a transducer arranged on the main front face; a step of depositing a dielectric encapsulation layer on the main front face of the piezoelectric substrate and on the transducer; and a step of assembling the dielectric encapsulation layer with the main front face of a support substrate having a coefficient of thermal expansion less than that of the piezoelectric substrate. In additional embodiments, a surface acoustic wave device comprises a layer of piezoelectric material equipped with a transducer on a main front face, arranged on a substrate support of which the coefficient of thermal expansion is less than that of the piezoelectric material. The transducer is arranged in a dielectric encapsulation layer, between the layer of piezoelectric material and the support substrate.
    Type: Application
    Filed: October 17, 2016
    Publication date: October 25, 2018
    Inventors: Pascal Guenard, Ionut Radu
  • Publication number: 20180159498
    Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
    Type: Application
    Filed: June 9, 2016
    Publication date: June 7, 2018
    Inventors: Arnaud Castex, Daniel Delprat, Bernard Aspar, Ionut Radu
  • Publication number: 20180105035
    Abstract: A filling pipe arrangement for filling an automobile fluid tank with fluid, especially aqueous urea solution, with a passage passing through a predetermined passageway along the filling pipe arrangement, wherein the passage extends from an inserting mouth to a discharge opening, wherein an inserting end section of the passage comprising the inserting mouth is designed to hold at least temporarily an output end section of a delivery device, such as a spigot, a Kruse bottle, or the like, wherein the passage comprises, at a distance from the inserting mouth, a conducting section designed to lead fluid introduced into the filling pipe arrangement through the filling pipe arrangement, wherein the filling pipe arrangement comprises a magnetic arrangement whose magnetic field reaches into the passage in one section of the passageway, the magnetic arrangement is received in the filling pipe arrangement so that it is movable along the passageway.
    Type: Application
    Filed: October 15, 2017
    Publication date: April 19, 2018
    Inventor: Andi-Ionut Radu
  • Patent number: 9905531
    Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: February 27, 2018
    Assignee: Soitec
    Inventors: Ionut Radu, Marcel Broekaart, Arnaud Castex, Gweltaz Gaudin, Gregory Riou
  • Publication number: 20170207164
    Abstract: Methods of forming a semiconductor structure include forming a device layer on an initial substrate, attaching a first surface of the device layer to a temporary substrate and forming a high resistivity layer on a second surface of the device layer by removing a portion of the initial substrate. Methods further include attaching a final substrate to the high resistivity layer and removing the temporary substrate. Semiconductor structures are fabricated by such methods that include a final substrate, a high resistivity layer disposed over the final substrate and a device layer disposed over the high resistivity layer.
    Type: Application
    Filed: January 13, 2017
    Publication date: July 20, 2017
    Inventors: Ionut Radu, Eric Desbonnets
  • Patent number: 9659777
    Abstract: The invention relates to a process for stabilizing a bonding interface, located within a structure for applications in the fields of electronics, optics and/or optoelectronics and that comprises an oxide layer buried between an active layer and a receiver substrate, the bonding interface having been obtained by molecular adhesion. In accordance with the invention, the process further comprises irradiating this structure with a light energy flux provided by a laser, so that the flux, directed toward the structure, is absorbed by the energy conversion layer and converted to heat in this layer, and in that this heat diffuses into the structure toward the bonding interface, so as to thus stabilize the bonding interface.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 23, 2017
    Assignee: Soitec
    Inventors: Didier Landru, Carole David, Ionut Radu, Lucianna Capello, Yann Sinquin
  • Patent number: 9553014
    Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: January 24, 2017
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 9548237
    Abstract: A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement region. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: January 17, 2017
    Assignee: SOITEC
    Inventors: Gweltaz Gaudin, Oleg Kononchuk, Ionut Radu
  • Publication number: 20160358805
    Abstract: The present disclosure relates to a method for mechanically separating layers, in particular in a double layer transfer process. The present disclosure relates more in particular to a method for mechanically separating layers, comprising the steps of providing a semiconductor compound comprising a layer of a handle substrate and an active layer with a front main side and a back main side opposite the front main side, wherein the layer of the handle substrate is attached to the front main side of the active layer, then providing a layer of a carrier substrate onto the back main side of the active layer, and then initiating mechanical separation of the layer of the handle substrate, wherein the layer of the handle substrate and the layer of the carrier substrate are provided with a substantially symmetrical mechanical structure.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 8, 2016
    Inventors: Marcel Broekaart, Ionut Radu, Didier Landru
  • Publication number: 20160197006
    Abstract: The disclosure relates to a process for locating devices, the process comprising the following steps: a) providing a carrier substrate comprising: a device layer; and alignment marks; b) providing a donor substrate; c) forming a weak zone in the donor substrate, the weak zone delimiting a useful layer; d) assembling the donor substrate and the carrier substrate; and e) fracturing the donor substrate in the weak zone so as to transfer the useful layer to the device layer; wherein the alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer.
    Type: Application
    Filed: June 24, 2014
    Publication date: July 7, 2016
    Inventors: Marcel Broekaart, Ionut Radu, Chrystelle Lagahe Blanchard
  • Publication number: 20160086974
    Abstract: Methods of fabricating a semiconductor structure include implanting ion into a second region of a strained semiconductor layer on a multi-layer substrate to amorphize a portion of crystalline semiconductor material in the second region of the strained semiconductor layer without amorphizing a first region of the strained semiconductor layer. The amorphous region is recrystallized, and elements are diffused within the semiconductor layer to enrich a concentration of the diffused elements in a portion of the second region of the strained semiconductor layer and alter a strain state therein relative to a strain state of the first region of the strained semiconductor layer. A first plurality of transistor channel structures are formed that each comprise a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures are formed that each comprise a portion of the second region of the semiconductor layer.
    Type: Application
    Filed: August 19, 2015
    Publication date: March 24, 2016
    Inventors: Mariam Sadaka, Bich-Yen Nguyen, Ionut Radu
  • Publication number: 20150364364
    Abstract: A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region.
    Type: Application
    Filed: January 28, 2013
    Publication date: December 17, 2015
    Inventors: Gweltaz Gaudin, Oleg Kononchuk, Ionut Radu
  • Patent number: 9165945
    Abstract: Methods of fabricating a semiconductor structure include implanting ion into a second region of a strained semiconductor layer on a multi-layer substrate to amorphize a portion of crystalline semiconductor material in the second region of the strained semiconductor layer without amorphizing a first region of the strained semiconductor layer. The amorphous region is recrystallized, and elements are diffused within the semiconductor layer to enrich a concentration of the diffused elements in a portion of the second region of the strained semiconductor layer and alter a strain state therein relative to a strain state of the first region of the strained semiconductor layer. A first plurality of transistor channel structures are formed that each comprise a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures are formed that each comprise a portion of the second region of the semiconductor layer.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: October 20, 2015
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Bich-Yen Nguyen, Ionut Radu
  • Publication number: 20150279830
    Abstract: The present invention relates to an apparatus for the manufacture of semiconductor devices wherein the apparatus includes a bonding module that has a vacuum chamber to provide bonding of wafers under pressure below atmospheric pressure; and a loadlock module connected to the bonding module and configured for wafer transfer to the bonding module. The loadlock module is also connected to a first vacuum pumping device configured to reduce the pressure in the loadlock module to below atmospheric pressure. The bonding and loadlock modules remain at a pressure below atmospheric pressure while the wafer is transferred from the loadlock module into the bonding module.
    Type: Application
    Filed: May 27, 2015
    Publication date: October 1, 2015
    Inventors: Marcel Broekaart, Ionut Radu
  • Patent number: 9138980
    Abstract: The present invention relates to an apparatus for the manufacture of semiconductor devices wherein the apparatus includes a bonding module that has a vacuum chamber to provide bonding of wafers under pressure below atmospheric pressure; and a loadlock module connected to the bonding module and configured for wafer transfer to the bonding module. The loadlock module is also connected to a first vacuum pumping device configured to reduce the pressure in the loadlock module to below atmospheric pressure. The bonding and loadlock modules remain at a pressure below atmospheric pressure while the wafer is transferred from the loadlock module into the bonding module.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: September 22, 2015
    Assignee: SOITEC
    Inventors: Marcel Broekaart, Ionut Radu
  • Patent number: 9136134
    Abstract: Methods of fabricating semiconductor devices include forming a metal silicide in a portion of a crystalline silicon layer, and etching the metal silicide using an etchant selective to the metal silicide relative to the crystalline silicon to provide a thin crystalline silicon layer. Silicon-on-insulator (SOI) substrates may be formed by providing a layer of crystalline silicon over a base substrate with a dielectric material between the layer of crystalline silicon and the base substrate, and thinning the layer of crystalline silicon by forming a metal silicide layer in a portion of the crystalline silicon, and then etching the metal silicide layer using an etchant selective to the metal silicide layer relative to the crystalline silicon.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: September 15, 2015
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Ionut Radu
  • Publication number: 20150228535
    Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
    Type: Application
    Filed: April 23, 2015
    Publication date: August 13, 2015
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 9087767
    Abstract: The invention relates to a process for manufacturing a semiconductor structure comprising a functionalized layer on a support substrate, comprising the following steps: (a) implanting ionic species in a source substrate comprising the said functionalized layer and a sacrificial buffer layer located under the functionalized layer relative to the direction of implantation, to a depth delimiting the thickness of an upper part of the source substrate comprising the functionalized layer and at least part of the buffer layer; (b) bonding the source substrate to the support substrate; (c) fracturing the source substrate and transferring the upper part of the source substrate to the support substrate; (d) removing the buffer layer by selective etching with respect to the functionalized layer.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: July 21, 2015
    Assignee: SOITEC
    Inventor: Ionut Radu
  • Publication number: 20150179603
    Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa.
    Type: Application
    Filed: June 5, 2013
    Publication date: June 25, 2015
    Inventors: Ionut Radu, Marcel Broekaart, Arnaud Castex, Gweltaz Gaudin, Gregory Riou
  • Patent number: 9041214
    Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 26, 2015
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Ionut Radu