Patents by Inventor Ionut Radu

Ionut Radu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120241821
    Abstract: A heterostructure that includes, successively, a support substrate of a material having an electrical resistivity of less than 10?3 ohm·cm and a thermal conductivity of greater than 100 W·m?1·K?1, a bonding layer, a first seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, a second seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and an active layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and being present in a thickness of between 3 and 100 micrometers. The materials of the support substrate, the bonding layer and the first seed layer are refractory at a temperature of greater than 750° C., the active layer and second seed layer have a difference in lattice parameter of less than 0.005 ?, the active layer is crack-free, and the heterostructure has a specific contact resistance between the bonding layer and the first seed layer that is less than or equal to 0.1 ohm·cm2.
    Type: Application
    Filed: December 1, 2010
    Publication date: September 27, 2012
    Applicant: SOITEC
    Inventors: Jean-Marc Bethoux, Fabrice Letertre, Chris Werkhoven, Ionut Radu, Oleg Kononchuck
  • Patent number: 8263475
    Abstract: A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method includes providing a silicon oxide layer with a thickness of less than or equal to 25 nanometers on one of a donor substrate or a receiver substrate or on both substrates, heat treating the substrate(s) that contains the silicon oxide layer at 900° C. to 1,200° C. under a neutral or reducing atmosphere that contains at least one of argon or hydrogen to form layer trapping through-holes inside the silicon oxide, bonding the substrates together at a bonding interface with the silicon oxide layer(s) positioned between them, reinforcing the bonding by annealing the substrates at 25° C. to 500° C. such that the trapping holes retaining gas species at the bonding interface, and transferring an active layer as a portion of the donor substrate onto the receiver substrate to obtain the heterostructure.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: September 11, 2012
    Assignee: Soitec
    Inventors: Ionut Radu, Oleg Kononchuk, Konstantin Bourdelle
  • Publication number: 20120067524
    Abstract: The present invention relates to an apparatus for the manufacture of semiconductor devices wherein the apparatus includes a bonding module that has a pumping device; a vacuum chamber connected to the pumping device; and an optical system configured to determine the position of alignment marks on the surfaces of the semiconductor wafers to be bonded in the bonding module. The apparatus also includes a loadlock module connected to the bonding module and configured for wafer transfer to the bonding module. The loadlock module is also connected to a first vacuum pumping device configured to reduce the pressure in the loadlock module to below atmospheric pressure.
    Type: Application
    Filed: November 29, 2011
    Publication date: March 22, 2012
    Inventors: Marcel Broekaart, Ionut Radu
  • Publication number: 20120013012
    Abstract: Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods.
    Type: Application
    Filed: July 15, 2010
    Publication date: January 19, 2012
    Inventors: Mariam Sadaka, Ionut Radu
  • Publication number: 20120013013
    Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
    Type: Application
    Filed: July 19, 2010
    Publication date: January 19, 2012
    Inventors: Mariam Sadaka, Ionut Radu
  • Publication number: 20120015497
    Abstract: A method of fabricating a heterostructure comprising at least a first substrate (120) made of sapphire and a second substrate (110) made of a material having a coefficient of thermal expansion that is different from that of the first substrate. The method includes a step (S6) of molecular bonding the second substrate (110) on the first substrate (120) made of sapphire. The method also includes, prior to bonding the two substrates together, a step (S1) of stoving the first substrate (120) at a temperature that lies in the range 100° C. to 500° C.
    Type: Application
    Filed: November 16, 2009
    Publication date: January 19, 2012
    Inventors: Gweltaz Gaudin, Mark Kennard, Matteo Piccin, Ionut Radu, Alexandre Vaufredaz
  • Publication number: 20110308721
    Abstract: The present invention relates to an apparatus for the manufacture of semiconductor devices wherein the apparatus includes a bonding module that has a vacuum chamber to provide bonding of wafers under pressure below atmospheric pressure; and a loadlock module connected to the bonding module and configured for wafer transfer to the bonding module. The loadlock module is also connected to a first vacuum pumping device configured to reduce the pressure in the loadlock module to below atmospheric pressure.
    Type: Application
    Filed: September 22, 2010
    Publication date: December 22, 2011
    Inventors: Marcel Broekaart, Ionut Radu
  • Publication number: 20110207295
    Abstract: A method for producing a structure having an ultra thin buried oxide (UTBOX) layer by assembling a donor substrate with a receiver substrate wherein at least one of the substrates includes an insulating layer having a thickness of less than 50 nm that faces the other substrate, conducting a first heat treatment for reinforcing the assembly between the two substrates at temperature below 400° C., and conducting a second heat treatment at temperature above 900° C., wherein the exposure time between 400° C. and 900° C. between the heat treatments is less than 1 minute and advantageously less than 30 seconds.
    Type: Application
    Filed: October 29, 2009
    Publication date: August 25, 2011
    Inventors: Didier Landru, Ionut Radu, Sébastien Vincent
  • Publication number: 20110127581
    Abstract: The present invention relates to a support for the epitaxy of a layer of a material of composition AlxInyGa(1-x-y)N, where 0?x?1, 0?y?1 and x+y?1, having successively from its base to its surface; a support substrate, a bonding layer, a monocrystalline seed layer for the epitaxial growth of the layer of material AlxInyGa(1-x-y)N. The support substrate is made of a material that presents an electrical resistivity of less than 10?3 ohm·cm and a thermal conductivity of greater than 100 W·m?1·K?1. The seed layer is in a material of the composition AlxInyGa(1-x-y)N, where 0?x?1, 0?y?1 and x+y?1. The seed and bonding layers provide a specific contact resistance that is less than or equal to 0.1 ohm·cm?2, and the materials of the support substrate, the bonding layer and the seed layer are refractory at a temperature of greater than 750° C. or even greater than 1000° C. The invention also relates to methods for manufacturing the support.
    Type: Application
    Filed: November 30, 2010
    Publication date: June 2, 2011
    Inventors: Jean-Marc Bethoux, Fabrice Letertre, Chris Werkhoven, Ionut Radu, Oleg Kononchuk
  • Publication number: 20100264458
    Abstract: A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method includes providing a silicon oxide layer with a thickness of less than or equal to 25 nanometers on one of a donor substrate or a receiver substrate or on both substrates, heat treating the substrate(s) that contains the silicon oxide layer at 900° C. to 1,200° C. under a neutral or reducing atmosphere that contains at least one of argon or hydrogen to form layer trapping through-holes inside the silicon oxide, bonding the substrates together at a bonding interface with the silicon oxide layer(s) positioned between them, reinforcing the bonding by annealing the substrates at 25° C. to 500° C. such that the trapping holes retaining gas species at the bonding interface, and transferring an active layer as a portion of the donor substrate onto the receiver substrate to obtain the heterostructure.
    Type: Application
    Filed: January 27, 2009
    Publication date: October 21, 2010
    Inventors: Ionut Radu, Oleg Kononchuk, Konstantin Bourdelle
  • Publication number: 20080145650
    Abstract: A method for bonding two substrates carried out in materials chosen from among semiconductor materials, includes the steps of bonding the two substrates by thermal treatment after plasma activation of the surface to be bonded for each substrate. One of the surfaces to be bonded includes an oxide layer. The plasma activation of the surface that has the oxide layer is carried out under an atmosphere containing oxygen, while the plasma activation of the surface to be bonded of the second substrate is carried out under an inert atmosphere.
    Type: Application
    Filed: May 30, 2007
    Publication date: June 19, 2008
    Inventors: Ionut Radu, Audrey Lambert