Patents by Inventor Isao Ozawa

Isao Ozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11854946
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding vires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: December 26, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Isao Ozawa
  • Publication number: 20220352053
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding vires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Application
    Filed: July 13, 2022
    Publication date: November 3, 2022
    Applicant: KIOXIA CORPORATION
    Inventor: Isao OZAWA
  • Patent number: 11424176
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: August 23, 2022
    Assignee: Kioxia Corporation
    Inventor: Isao Ozawa
  • Publication number: 20220044987
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Application
    Filed: November 19, 2020
    Publication date: February 10, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Isao OZAWA
  • Publication number: 20210074609
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 11, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Isao OZAWA
  • Patent number: 10872844
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: December 22, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Isao Ozawa
  • Patent number: 10566274
    Abstract: According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: February 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Isao Ozawa, Isao Maeda, Yasuo Kudo, Koichi Nagai, Katsuya Murakami
  • Publication number: 20190295928
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Application
    Filed: June 12, 2019
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Isao OZAWA
  • Patent number: 10409338
    Abstract: A semiconductor device package includes a substrate including, on an edge thereof, a connector that is connectable to a host, a nonvolatile semiconductor memory device disposed on a surface of the substrate, a memory controller disposed on the surface of the substrate, an oscillator disposed on the surface of the substrate and electrically connected to the memory controller, and a seal member sealing the nonvolatile semiconductor memory device, the memory controller, and the oscillator on the surface of the substrate.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: September 10, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Manabu Matsumoto, Katsuya Murakami, Akira Tanimoto, Isao Ozawa, Yuji Karakane, Tadashi Shimazaki
  • Patent number: 10366942
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: July 30, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Isao Ozawa
  • Patent number: 10297571
    Abstract: According to one embodiment, a semiconductor package includes a substrate with first and second pad, first semiconductor chip above the substrate, first wire, first mold member, second semiconductor chip above the first mold member, third semiconductor chip above the second semiconductor chip, second wire, and a second mold member. The first wire electrically connects the first pad and the first semiconductor chip. The first mold member seals the first wire and the first semiconductor chip. The second wire electrically connects the second pad and the second semiconductor chip. The second mold member seals the second wire, the second and the third semiconductor chips, and the first mold member.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: May 21, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Isao Ozawa
  • Patent number: 10204661
    Abstract: A semiconductor device includes a printed circuit board having a first surface and a second surface on a side opposite to the first surface. First pads are on the first surface of the printed circuit board. An interface part is mounted on the printed circuit board via the first pads and is configured to transfer a signal between the interface part and a host device. Second pads are also on the first surface and insulated from the interface part. A semiconductor memory and a controller are mounted on the first surface. First solder balls electrically connect the first pads and the controller. Second solder balls electrical connect the second pads and the controller. A plurality of third pads are disposed on the second surface and electrically connected to the second pads allowing direct connections to the controller and memory via the second pads.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: February 12, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Manabu Matsumoto, Isao Ozawa
  • Publication number: 20180315695
    Abstract: According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.
    Type: Application
    Filed: July 6, 2018
    Publication date: November 1, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Isao OZAWA, Isao MAEDA, Yasuo KUDO, Koichi NAGAI, Katsuya MURAKAMI
  • Patent number: 10090235
    Abstract: According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Isao Ozawa, Isao Maeda, Yasuo Kudo, Koichi Nagai, Katsuya Murakami
  • Patent number: 9911502
    Abstract: According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: March 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Koichi Nagai, Katsuya Murakami, Shinji Honjo, Satoru Fukuchi, Akira Tanimoto, Isao Ozawa
  • Publication number: 20170203239
    Abstract: A water treatment method used in a water treatment device including a filter for filtering untreated water and a housing that houses the filter includes a step of putting the untreated water into the housing to obtain filtered water that has permeated through the filter, and a step of replacing the untreated water in the housing by storage water. The storage water is water having less favorable survival conditions for microbes than the untreated water.
    Type: Application
    Filed: August 19, 2015
    Publication date: July 20, 2017
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Isao OZAWA, Kenichiro MIYATAKE, Munetsugu UEYAMA
  • Patent number: 9704593
    Abstract: According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: July 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Nagai, Katsuya Murakami, Shinji Honjo, Satoru Fukuchi, Akira Tanimoto, Isao Ozawa
  • Patent number: 9688376
    Abstract: Provided are a system and a method for treating ballast water for a ship, the system including a rotary filtration apparatus including a filter that is cylindrically formed so as to surround an axis, that is rotatable around the axis, and that has a pleated shape that is folded in a cylinder radial direction; and an electric motor for rotating the filter. A distance between the cleaning nozzle and a recess of the filter is 120 mm or less. The system and the method are configured to perform a steady-state operation that satisfies the following conditions a to d: a) a rotation speed of the filter during a filtering operation is in the range of 20 to 100 rpm, b) a flow speed of cleaning water ejected from the cleaning nozzle is 250 m/min or more, c) a flow rate of filtered water per unit area of the filter is 5.1 m/h or less, and d) a flow rate of discharged water discharged from the discharge channel is 5% of the flow rate of filtered water or more.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: June 27, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Munetsugu Ueyama, Isao Ozawa, Kenichiro Miyatake, Ryusuke Nakai
  • Patent number: D778850
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Manabu Matsumoto, Isao Ozawa
  • Patent number: D778852
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Manabu Matsumoto, Isao Ozawa