Patents by Inventor Isao Ozawa
Isao Ozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11854946Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding vires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.Type: GrantFiled: July 13, 2022Date of Patent: December 26, 2023Assignee: KIOXIA CORPORATIONInventor: Isao Ozawa
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Publication number: 20220352053Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding vires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.Type: ApplicationFiled: July 13, 2022Publication date: November 3, 2022Applicant: KIOXIA CORPORATIONInventor: Isao OZAWA
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Patent number: 11424176Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.Type: GrantFiled: November 19, 2020Date of Patent: August 23, 2022Assignee: Kioxia CorporationInventor: Isao Ozawa
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Publication number: 20220044987Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.Type: ApplicationFiled: November 19, 2020Publication date: February 10, 2022Applicant: TOSHIBA MEMORY CORPORATIONInventor: Isao OZAWA
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Publication number: 20210074609Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.Type: ApplicationFiled: November 19, 2020Publication date: March 11, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventor: Isao OZAWA
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Patent number: 10872844Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.Type: GrantFiled: June 12, 2019Date of Patent: December 22, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Isao Ozawa
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Patent number: 10566274Abstract: According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.Type: GrantFiled: July 6, 2018Date of Patent: February 18, 2020Assignee: Toshiba Memory CorporationInventors: Isao Ozawa, Isao Maeda, Yasuo Kudo, Koichi Nagai, Katsuya Murakami
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Publication number: 20190295928Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.Type: ApplicationFiled: June 12, 2019Publication date: September 26, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Isao OZAWA
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Patent number: 10409338Abstract: A semiconductor device package includes a substrate including, on an edge thereof, a connector that is connectable to a host, a nonvolatile semiconductor memory device disposed on a surface of the substrate, a memory controller disposed on the surface of the substrate, an oscillator disposed on the surface of the substrate and electrically connected to the memory controller, and a seal member sealing the nonvolatile semiconductor memory device, the memory controller, and the oscillator on the surface of the substrate.Type: GrantFiled: March 1, 2016Date of Patent: September 10, 2019Assignee: Toshiba Memory CorporationInventors: Manabu Matsumoto, Katsuya Murakami, Akira Tanimoto, Isao Ozawa, Yuji Karakane, Tadashi Shimazaki
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Patent number: 10366942Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.Type: GrantFiled: February 9, 2015Date of Patent: July 30, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventor: Isao Ozawa
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Patent number: 10297571Abstract: According to one embodiment, a semiconductor package includes a substrate with first and second pad, first semiconductor chip above the substrate, first wire, first mold member, second semiconductor chip above the first mold member, third semiconductor chip above the second semiconductor chip, second wire, and a second mold member. The first wire electrically connects the first pad and the first semiconductor chip. The first mold member seals the first wire and the first semiconductor chip. The second wire electrically connects the second pad and the second semiconductor chip. The second mold member seals the second wire, the second and the third semiconductor chips, and the first mold member.Type: GrantFiled: January 23, 2014Date of Patent: May 21, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventor: Isao Ozawa
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Patent number: 10204661Abstract: A semiconductor device includes a printed circuit board having a first surface and a second surface on a side opposite to the first surface. First pads are on the first surface of the printed circuit board. An interface part is mounted on the printed circuit board via the first pads and is configured to transfer a signal between the interface part and a host device. Second pads are also on the first surface and insulated from the interface part. A semiconductor memory and a controller are mounted on the first surface. First solder balls electrically connect the first pads and the controller. Second solder balls electrical connect the second pads and the controller. A plurality of third pads are disposed on the second surface and electrically connected to the second pads allowing direct connections to the controller and memory via the second pads.Type: GrantFiled: March 2, 2015Date of Patent: February 12, 2019Assignee: Toshiba Memory CorporationInventors: Manabu Matsumoto, Isao Ozawa
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Publication number: 20180315695Abstract: According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.Type: ApplicationFiled: July 6, 2018Publication date: November 1, 2018Applicant: Toshiba Memory CorporationInventors: Isao OZAWA, Isao MAEDA, Yasuo KUDO, Koichi NAGAI, Katsuya MURAKAMI
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Patent number: 10090235Abstract: According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.Type: GrantFiled: February 19, 2014Date of Patent: October 2, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Isao Ozawa, Isao Maeda, Yasuo Kudo, Koichi Nagai, Katsuya Murakami
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Patent number: 9911502Abstract: According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode.Type: GrantFiled: June 14, 2017Date of Patent: March 6, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Koichi Nagai, Katsuya Murakami, Shinji Honjo, Satoru Fukuchi, Akira Tanimoto, Isao Ozawa
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Publication number: 20170203239Abstract: A water treatment method used in a water treatment device including a filter for filtering untreated water and a housing that houses the filter includes a step of putting the untreated water into the housing to obtain filtered water that has permeated through the filter, and a step of replacing the untreated water in the housing by storage water. The storage water is water having less favorable survival conditions for microbes than the untreated water.Type: ApplicationFiled: August 19, 2015Publication date: July 20, 2017Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Isao OZAWA, Kenichiro MIYATAKE, Munetsugu UEYAMA
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Patent number: 9704593Abstract: According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode.Type: GrantFiled: March 9, 2015Date of Patent: July 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Koichi Nagai, Katsuya Murakami, Shinji Honjo, Satoru Fukuchi, Akira Tanimoto, Isao Ozawa
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Patent number: 9688376Abstract: Provided are a system and a method for treating ballast water for a ship, the system including a rotary filtration apparatus including a filter that is cylindrically formed so as to surround an axis, that is rotatable around the axis, and that has a pleated shape that is folded in a cylinder radial direction; and an electric motor for rotating the filter. A distance between the cleaning nozzle and a recess of the filter is 120 mm or less. The system and the method are configured to perform a steady-state operation that satisfies the following conditions a to d: a) a rotation speed of the filter during a filtering operation is in the range of 20 to 100 rpm, b) a flow speed of cleaning water ejected from the cleaning nozzle is 250 m/min or more, c) a flow rate of filtered water per unit area of the filter is 5.1 m/h or less, and d) a flow rate of discharged water discharged from the discharge channel is 5% of the flow rate of filtered water or more.Type: GrantFiled: February 8, 2013Date of Patent: June 27, 2017Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Munetsugu Ueyama, Isao Ozawa, Kenichiro Miyatake, Ryusuke Nakai
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Patent number: D778850Type: GrantFiled: May 13, 2016Date of Patent: February 14, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Manabu Matsumoto, Isao Ozawa
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Patent number: D778852Type: GrantFiled: May 13, 2016Date of Patent: February 14, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Manabu Matsumoto, Isao Ozawa