Substrate for an electronic circuit

- Kabushiki Kaisha Toshiba
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Description

FIG. 1 is a perspective view of a substrate for an electronic circuit showing our new design;

FIG. 2 is a rear perspective view thereof;

FIG. 3 is a front elevational view thereof;

FIG. 4 is a rear elevational view thereof;

FIG. 5 is a right side elevational view, a left side elevational view being a mirror image thereof;

FIG. 6 is a top plan view thereof; and,

FIG. 7 is a bottom plan view thereof.

The broken lines shown in the drawings represent portions of the substrate for an electronic circuit that form no part of the claimed design.

Claims

The ornamental design for a substrate for an electronic circuit, as shown and described.

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Patent History
Patent number: D778852
Type: Grant
Filed: May 13, 2016
Date of Patent: Feb 14, 2017
Assignee: Kabushiki Kaisha Toshiba (Minato-ku, Tokyo)
Inventors: Manabu Matsumoto (Yokohama), Isao Ozawa (Chigasaki)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/564,531