Patents by Inventor Isao Ozawa

Isao Ozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170010639
    Abstract: A semiconductor device package includes a substrate including, on an edge thereof, a connector that is connectable to a host, a nonvolatile semiconductor memory device disposed on a surface of the substrate, a memory controller disposed on the surface of the substrate, an oscillator disposed on the surface of the substrate and electrically connected to the memory controller, and a seal member sealing the nonvolatile semiconductor memory device, the memory controller, and the oscillator on the surface of the substrate.
    Type: Application
    Filed: March 1, 2016
    Publication date: January 12, 2017
    Inventors: Manabu MATSUMOTO, Katsuya MURAKAMI, Akira TANIMOTO, Isao OZAWA, Yuji KARAKANE, Tadashi SHIMAZAKI
  • Patent number: 9543271
    Abstract: A semiconductor device includes a substrate, a semiconductor memory unit mounted on a surface of the substrate, a memory controller configured to control the semiconductor memory unit and mounted on the surface of the substrate adjacent to the semiconductor memory unit, and a sealing layer disposed on the surface of the substrate and covering the semiconductor memory unit and the memory controller.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: January 10, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Manabu Matsumoto, Akira Tanimoto, Isao Ozawa
  • Publication number: 20160268229
    Abstract: A semiconductor device includes a substrate, a semiconductor memory unit mounted on a surface of the substrate, a memory controller configured to control the semiconductor memory unit and mounted on the surface of the substrate adjacent to the semiconductor memory unit, and a sealing layer disposed on the surface of the substrate and covering the semiconductor memory unit and the memory controller.
    Type: Application
    Filed: August 27, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Manabu MATSUMOTO, Akira TANIMOTO, Isao OZAWA
  • Publication number: 20160125950
    Abstract: According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode.
    Type: Application
    Filed: March 9, 2015
    Publication date: May 5, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi NAGAI, Katsuya Murakami, Shinji Honjo, Satoru Fukuchi, Akira Tanimoto, Isao Ozawa
  • Publication number: 20160114269
    Abstract: A filtering device includes, as a filter membrane, a pleated filter formed of a filter base having folds so as to repeat peak portions and valley portions, the pleated filter having a shape of a cylinder whose axial direction is a ridge line direction of the folds. In the filtering device, the pleated filter is rotatable about a cylindrical axis of the shape of the cylinder. The filtering device includes a nozzle that is provided so as to face an outer circumferential surface of the pleated filter and that ejects a liquid toward the outer circumferential surface.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 28, 2016
    Inventors: Shinichi KANAZAWA, Isao OZAWA
  • Patent number: 9275947
    Abstract: A semiconductor device includes a substrate, a sealing portion, a controller, a semiconductor chip, and a plurality of differential signal balls. The substrate has a first surface and a second surface positioned on a side opposite to the first surface. The sealing portion is formed on the first surface of the substrate. The controller is covered with the sealing portion. The semiconductor chip is electrically connected to the controller, and is covered with the sealing portion. The plurality of differential signal balls are formed on the second surface of the substrate. At least some of the plurality of differential signal balls are arranged substantially parallel to one side of the substrate.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: March 1, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Ozawa, Isao Maeda, Yasuo Kudo, Koichi Nagai, Katsuya Murakami, Akira Tanimoto
  • Publication number: 20150380061
    Abstract: A semiconductor device includes a printed circuit board having a first surface and a second surface on a side opposite to the first surface. First pads are on the first surface of the printed circuit board. An interface part is mounted on the printed circuit board via the first pads and is configured to transfer a signal between the interface part and a host device. Second pads are also on the first surface and insulated from the interface part. A semiconductor memory and a controller are mounted on the first surface. First solder balls electrically connect the first pads and the controller. Second solder balls electrical connect the second pads and the controller. A plurality of third pads are disposed on the second surface and electrically connected to the second pads allowing direct connections to the controller and memory via the second pads.
    Type: Application
    Filed: March 2, 2015
    Publication date: December 31, 2015
    Inventors: Manabu MATSUMOTO, Isao OZAWA
  • Publication number: 20150380062
    Abstract: According to the embodiments, there are provided semiconductor memories that are mounted individually on two sides of a mounting board; a controller that is mounted either on an obverse side or a reverse side of the mounting board, and performs read and write control of the semiconductor memories; and a connector that is deviated in a lateral direction from the controller so as not to overlap the controller, is mounted either on the obverse side or the reverse side of the mounting board, and transfers a signal exchanged between the controller and outside.
    Type: Application
    Filed: September 10, 2015
    Publication date: December 31, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasuyuki Nagahara, Isao Ozawa
  • Publication number: 20150336651
    Abstract: A ballast water treatment apparatus includes a cylindrical pleated filter that is rotatably held about an axis of a cylinder, a driving mechanism that rotates the pleated filter, an untreated water nozzle that ejects untreated water toward an outer circumferential surface of the pleated filter, a case that is provided so as to surround the pleated filter and that includes an outer cylindrical portion including a nozzle opening of the untreated water nozzle therein, a filtered water flow path that guides filtered water that has permeated through the pleated filter from the inside of the cylinder of the pleated filter to the outside of the case, and a discharge flow path that discharges discharged water that has not been filtered by the pleated filter to the outside of the case. The ballast water treatment apparatus further includes a reverse cleaning mechanism that supplies cleaning water to the inside of the cylinder of the pleated filter through the filtered water flow path.
    Type: Application
    Filed: December 19, 2013
    Publication date: November 26, 2015
    Inventors: Ryoji HARADA, Munetsugu UEYAMA, Shinichi KANAZAWA, Satoshi YAHAGI, Isao OZAWA
  • Patent number: 9173293
    Abstract: According to the embodiments, there are provided semiconductor memories that are mounted individually on two sides of a mounting board; a controller that is mounted either on an obverse side or a reverse side of the mounting board, and performs read and write control of the semiconductor memories; and a connector that is deviated in a lateral direction from the controller so as not to overlap the controller, is mounted either on the obverse side or the reverse side of the mounting board, and transfers a signal exchanged between the controller and outside.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: October 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Nagahara, Isao Ozawa
  • Patent number: 9087831
    Abstract: According to one embodiment, a semiconductor module includes a semiconductor chip that is mounted on a printed substrate, a terminal electrode that is formed on the printed substrate so as to be electrically connected to the semiconductor chip, a metal coating layer that is formed on the terminal electrode, a plating lead wire that is electrically connected to the terminal electrode, and a gap that is formed in the plating lead wire.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: July 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Isao Ozawa
  • Publication number: 20150200008
    Abstract: According to one embodiment, a semiconductor package includes a package substrate, a controller chip, a semiconductor memory chip, a temperature sensor, a seal portion, and a plurality of solder balls. The controller chip and the semiconductor memory chip are provided on a first surface of the package substrate. The temperature sensor is provided at a position along an edge of the first surface, which is at a center portion separated away from corner portions. The plurality of solder balls is provided on a second surface that is at an opposite side of the first surface.
    Type: Application
    Filed: July 1, 2014
    Publication date: July 16, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Isao OZAWA, Akira TANIMOTO, Eigo MATSUURA, Katsuya MURAKAMI, Yasuo KUDO, Koichi NAGAI
  • Publication number: 20150155225
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Application
    Filed: February 9, 2015
    Publication date: June 4, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Isao OZAWA
  • Publication number: 20150137363
    Abstract: A semiconductor device includes a substrate, a sealing portion, a controller, a semiconductor chip, and a plurality of differential signal balls. The substrate has a first surface and a second surface positioned on a side opposite to the first surface. The sealing portion is formed on the first surface of the substrate. The controller is covered with the sealing portion. The semiconductor chip is electrically connected to the controller, and is covered with the sealing portion. The plurality of differential signal balls are formed on the second surface of the substrate. At least some of the plurality of differential signal balls are arranged substantially parallel to one side of the substrate.
    Type: Application
    Filed: February 26, 2014
    Publication date: May 21, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Isao OZAWA, Isao MAEDA, Yasuo KUDO, Koichi NAGAI, Katsuya MURAKAMI, Akira TANIMOTO
  • Publication number: 20150130059
    Abstract: According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.
    Type: Application
    Filed: February 19, 2014
    Publication date: May 14, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Isao OZAWA, Isao MAEDA, Yasuo KUDO, Koichi NAGAI, Katsuya MURAKAMI
  • Publication number: 20150069632
    Abstract: According to one embodiment, a semiconductor package includes a substrate with first and second pad, first semiconductor chip above the substrate, first wire, first mold member, second semiconductor chip above the first mold member, third semiconductor chip above the second semiconductor chip, second wire, and a second mold member. The first wire electrically connects the first pad and the first semiconductor chip. The first mold member seals the first wire and the first semiconductor chip. The second wire electrically connects the second pad and the second semiconductor chip. The second mold member seals the second wire, the second and the third semiconductor chips, and the first mold member.
    Type: Application
    Filed: January 23, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Isao OZAWA
  • Patent number: 8970019
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Isao Ozawa
  • Patent number: D730304
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Manabu Matsumoto, Isao Ozawa
  • Patent number: D764424
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 23, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Manabu Matsumoto, Isao Ozawa
  • Patent number: D778851
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Manabu Matsumoto, Isao Ozawa