Patents by Inventor Itaru Kanno

Itaru Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8569136
    Abstract: A manufacturing method of a semiconductor device is provided which can improve the performance of the semiconductor device. Ion implantation is applied to nMIS regions 1A and 1B and pMIS regions 1C and 1D of a semiconductor substrate 1 with offset spacers formed over sidewalls of gate electrodes GE1, GE2, GE3, and GE4 to thereby form extension regions for source and drain. In this case, a different photoresist pattern is used for each of the nMIS regions 1A and 1B and the pMIS regions 1C and 1D to individually perform the corresponding ion implantation. Every time the photoresist pattern is re-created, the offset spacer is also re-created.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: October 29, 2013
    Assignee: Renesas Electronic Corporation
    Inventor: Itaru Kanno
  • Publication number: 20120258576
    Abstract: A manufacturing method of a semiconductor device is provided which can improve the performance of the semiconductor device. Ion implantation is applied to nMIS regions 1A and 1B and pMIS regions 1C and 1D of a semiconductor substrate 1 with offset spacers formed over sidewalls of gate electrodes GE1, GE2, GE3, and GE4 to thereby form extension regions for source and drain. In this case, a different photoresist pattern is used for each of the nMIS regions 1A and 1B and the pMIS regions 1C and 1D to individually perform the corresponding ion implantation. Every time the photoresist pattern is re-created, the offset spacer is also re-created.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 11, 2012
    Inventor: Itaru KANNO
  • Publication number: 20110298097
    Abstract: A semiconductor device is provided wherein stacked semiconductor substrates are electrically coupled together in a satisfactory state by a conductor buried in the interior of a through hole. A first semiconductor substrate includes a substrate having main surfaces, further includes a semiconductor element formed within and over the substrate, a wiring coupled to the semiconductor element electrically, and a conductive layer formed in the interior of a through hole, the through hole extending through mutually confronting first and second main surfaces as the main surfaces of the substrate and reaching the wiring. The first semiconductor substrate and a second semiconductor substrate are stacked and the conductive layer is coupled to a wiring of the second semiconductor substrate electrically. In a second main surface of the conductive layer, a recess is formed around an end portion of the through hole so that a bottom wall surface of the recess is present in the interior of the substrate.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 8, 2011
    Inventors: Manabu Sueyoshi, Seiji Muranaka, Tomoryo Shono, Itaru Kanno
  • Patent number: 8037891
    Abstract: An object of the present is to uniform particle diameters and speeds of liquid droplets in a two-fluid nozzle for cleaning substrates which mixes gas and liquid internally and injects liquid droplets with gas so as to clean a substrate. The two-fluid nozzle for cleaning substrates has a gas supply passage for supplying gas, a liquid supply passage for supplying liquid, and a lead-out passage for leading out internally-formed liquid droplets, wherein an injection port for injecting liquid droplets to the outside is formed at the front end of the lead-out passage, and wherein a cross-sectional area Sb of the injection port is formed smaller than a cross-sectional area Sa of the lead-out passage, and a cross sectional area Sc of an exit of the gas supply passage is formed smaller than the cross-sectional area Sa of the lead-out passage.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: October 18, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Itaru Kanno, Yusaku Hirota, Kenji Sekiguchi, Hiroshi Nagayasu, Shouichi Shimose
  • Publication number: 20100330794
    Abstract: There is provided a method for cleaning a semiconductor device capable of making compatible the inhibition of dissolution of a gate metal material and the acquisition of a favorable contact resistance.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 30, 2010
    Inventors: Hirokazu KURISU, Yutaka Takeshima, Itaru Kanno, Masahiko Higashi, Yusaku Hirota
  • Publication number: 20100178764
    Abstract: A method for fabricating a semiconductor device, includes the steps of (a) forming a metal film containing a precious metal on a substrate having a semiconductor layer containing silicon or on a conductive film containing silicon formed on the substrate, (b) after step (a), heat-treating the substrate to allow the precious metal to react with silicon to form a silicide film containing the precious metal on the substrate or the conductive film, (c) after step (b), forming an oxide film on a portion of the silicide film underlying an unreacted portion of the precious metal using a first chemical solution, and (d) dissolving the unreacted portion of the precious metal using a second chemical solution.
    Type: Application
    Filed: January 13, 2010
    Publication date: July 15, 2010
    Inventors: Kenji NARITA, Yoshiharu Hidaka, Koji Utaka, Takao Yamaguchi, Itaru Kanno, Hirokazu Kurisu
  • Publication number: 20090218694
    Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.
    Type: Application
    Filed: February 20, 2009
    Publication date: September 3, 2009
    Inventors: Takahiko KATO, Hiroshi NAKANO, Haruo AKAHOSHI, Yuuji TAKADA, Yoshimi SUDO, Tetsuo FUJIWARA, Itaru KANNO, Tomoryo SHONO, Yukinori HIROSE
  • Publication number: 20090137118
    Abstract: Initially, an interconnection 5w that contains copper is formed on a semiconductor substrate 1 (step (A)). On the interconnection 5w, an etching stopper film 6es is formed (step (B)). On the etching stopper film 6es, an insulating layer 6 is formed (step (C)). In the insulating layer 6, a via hole 6v that reaches the etching stopper film 6es is formed (step (D)). A surface of each of via hole 6v and the insulating layer 6 is cleaned with an organic solvent C (step (E)). The etching stopper film 6es is removed such that the interconnection 5w is exposed (step (F)). An interconnection 6w that electrically connects to the exposed interconnection 5w is further formed (step (G)). It is thereby possible to obtain a method of manufacturing a semiconductor device, including a cleaning step that can suppress corrosion of an interconnection that contains copper.
    Type: Application
    Filed: October 9, 2008
    Publication date: May 28, 2009
    Inventors: Yusaku Hirota, Itaru Kanno
  • Patent number: 7537987
    Abstract: In a semiconductor device manufacturing method of the invention, a metal film, for forming a gate electrode, is formed on a gate insulating film. Subsequently, when the metal film is processed, part of the metal film is removed by a wet etching process using a given chemical liquid.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: May 26, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masahiko Higashi, Satoshi Kume, Jiro Yugami, Shinichi Yamanari, Takahiro Maruyama, Itaru Kanno
  • Publication number: 20090014028
    Abstract: There is provided a method of efficiently cleaning substrates without damaging a fine pattern formed thereon. It is a method of cleaning one or more substrates in a system processing one or more substrates as one batch by dipping one or more substrates as one batch, including the steps of: immersing one or more substrates as one batch in a wet etching solution; ultrasonically cleaning one or more substrates as one batch; and drying one or more substrates as one batch. The step of ultrasonically cleaning employs a cleaning solution having a gas dissolved therein to have a degree of saturation of 60% to 100% at an atmospheric pressure, and an ultrasonic wave having a frequency of at least 500 kHz and an energy of 0.02 W/cm2 to 0.5 W/cm2.
    Type: Application
    Filed: July 10, 2008
    Publication date: January 15, 2009
    Inventors: Yusaku Hirota, Itaru Kanno, Hiroshi Morita, Junichi Ida
  • Patent number: 7250391
    Abstract: The cleaning composition for removing resists includes a salt of hydrofluoric acid and a base not containing a metal (A component), a water-soluble organic solvent (B1 component), at least one organic acid or inorganic acid (C component), water (D component), and, optionally, an ammonium salt (E1 component), and having a pH 4-8. Thus, in manufacturing a semiconductor device, such as a copper interconnecting process, efficiency of removing resist residue and other etching residue after etching or ashing is improved, and corrosion resistance of a copper and an insulating film is also improved.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: July 31, 2007
    Assignees: Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd., EKC Technology K.K.
    Inventors: Itaru Kanno, Yasuhiro Asaoka, Masahiko Higashi, Yoshiharu Hidaka, Etsuro Kishio, Tetsuo Aoyama, Tomoko Suzuki, Toshitaka Hiraga, Toshihiko Nagai
  • Publication number: 20070141849
    Abstract: An object of the present is to uniform particle diameters and speeds of liquid droplets in a two-fluid nozzle for cleaning substrates which mixes gas and liquid internally and injects liquid droplets with gas so as to clean a substrate. The two-fluid nozzle for cleaning substrates has a gas supply passage for supplying gas, a liquid supply passage for supplying liquid, and a lead-out passage for leading out internally-formed liquid droplets, wherein an injection port for injecting liquid droplets to the outside is formed at the front end of the lead-out passage, and wherein a cross-sectional area Sb of the injection port is formed smaller than a cross-sectional area Sa of the lead-out passage, and a cross sectional area Sc of an exit of the gas supply passage is formed smaller than the cross-sectional area Sa of the lead-out passage.
    Type: Application
    Filed: March 9, 2005
    Publication date: June 21, 2007
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Itaru Kanno, Yusaku Hirota, Kenji Sekiguchi, Hiroshi Nagayasu, Shouichi Shimose
  • Publication number: 20070099406
    Abstract: In a semiconductor device manufacturing method of the invention, a metal film, for forming a gate electrode, is formed on a gate insulating film. Subsequently, when the metal film is processed, part of the metal film is removed by a wet etching process using a given chemical liquid.
    Type: Application
    Filed: October 23, 2006
    Publication date: May 3, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Masahiko Higashi, Satoshi Kume, Jiro Yugami, Shinichi Yamanari, Takahiro Maruyama, Itaru Kanno
  • Publication number: 20040106531
    Abstract: The cleaning composition for removing resists includes a salt of hydrofluoric acid and a base not containing a metal (A component), a water-soluble organic solvent (B1 component), at least one acid selected from a group consisting of organic acid and inorganic acid (C component), water (D component), and optionally an ammonium salt (E1 component), and its hydrogen ion concentration (pH) is 4-8. Thus, in the manufacturing process of a semiconductor device such as a copper interconnecting process, removing efficiency of resist residue and other etching residue after etching or ashing improves, and corrosion resistance of copper and insulating film also improves.
    Type: Application
    Filed: July 11, 2003
    Publication date: June 3, 2004
    Applicants: Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd., EKC Technology K.K.
    Inventors: Itaru Kanno, Yasuhiro Asaoka, Masahiko Higashi, Yoshiharu Hidaka, Etsuro Kishio, Tetsuo Aoyama, Tomoko Suzuki, Toshitaka Hiraga, Toshihiko Nagai
  • Patent number: 6730239
    Abstract: A cleaning agent for a semiconductor device contains a hydroxide, water and a compound expressed in the following general formula (I) and/or the following general formula (II): HO—((EO)x—(PO)y)z—H  (I) R—[(EO)x—(PO)y)z—H]m  (II) Thus provided is a cleaning agent for a semiconductor device, which is so improved as not to disconnect a wire or an embedded conductive layer.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: May 4, 2004
    Assignees: Renesas Technology Corp., Sumitomo Chemical Company, Limited
    Inventors: Itaru Kanno, Naoki Yokoi, Hiroshi Morita, Naoki Ichiki, Hideaki Nezu, Masayuki Takashima
  • Patent number: 6713232
    Abstract: Resist residues, which is formed in a process of forming Al interconnections, are removed through use of a single chemical. A chemical which contains an organic acid or a salt thereof and water and which has a pH below 8 is used as a treatment for removing resist or resist residues. The chemical may be used in a process in which Al, W, Ti, TiN, and SiO2 are exposed on the surface of a wafer after etching of an Al interconnection; in a process in which Al, W, Ti, TiN, and SiO2 are exposed on the surface of a wafer after etching a hole reaching an Al interconnection in an dielectric layer; in a process in which Cu is exposed on the surface of a semiconductor wafer after dry-etching of a Cu interconnection or etching of an interlayer dielectric film laid on a Cu interconnection; and in a process in which metal material such as W, WN, Ti, or TiN; poly-Si; SiN; and SiO2 are exposed on the surface of a wafer after etching of a metal gate.
    Type: Grant
    Filed: December 4, 2000
    Date of Patent: March 30, 2004
    Assignee: Kao Corporation
    Inventors: Seiji Muranaka, Itaru Kanno, Mami Shirota, Junji Kondo
  • Patent number: 6708903
    Abstract: A two-fluid cleaning jet nozzle comprises a mixing part mixing two types of externally supplied fluids with each other for preparing a fluid mixture, a straight pipe linearly and tubularly formed along a prescribed accelerating direction toward the surface of a cleaned substance for accelerating the aforementioned fluid mixture received from the mixing part along the aforementioned accelerating direction, and a bent part connected to an outlet of the straight pipe. The bent part has an inner surface communicating with the inner surface of the straight pipe. The inner surface of the bent part defines a convexly bent curved surface to spread outward with respect to a space receiving the fluid mixture injected from the straight pipe.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: March 23, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Itaru Kanno
  • Publication number: 20040016447
    Abstract: The present invention provides a cleaning equipment provided with a cleaning solution tank, a cleaning solution supply route for supplying the cleaning solution stored in the cleaning solution tank to a cleaning bath, a cleaning solution return route for returning the cleaning solution that has been supplied to the cleaning bath to the cleaning solution tank, a gas supply route for supplying a purge gas into the cleaning solution tank, and a gas discharge route for discharging the purge gas from the cleaning solution tank. Moreover, a cleaning solution discharge opening of the cleaning solution return route is immersed in the cleaning solution stored in the cleaning solution tank.
    Type: Application
    Filed: January 27, 2003
    Publication date: January 29, 2004
    Applicants: Matsushita Electrical Industrial Co., Ltd., Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiko Nagai, Itaru Kanno, Naoki Yokoi, Yasuhiro Asaoka, Masahiko Higashi
  • Publication number: 20030089799
    Abstract: A two-fluid cleaning jet nozzle comprises a mixing part mixing two types of externally supplied fluids with each other for preparing a fluid mixture, a straight pipe linearly and tubularly formed along a prescribed accelerating direction toward the surface of a cleaned substance for accelerating the aforementioned fluid mixture received from the mixing part along the aforementioned accelerating direction, and a bent part connected to an outlet of the straight pipe. The bent part has an inner surface communicating with the inner surface of the straight pipe. The inner surface of the bent part defines a convexly bent curved surface to spread outward with respect to a space receiving the fluid mixture injected from the straight pipe.
    Type: Application
    Filed: May 17, 2002
    Publication date: May 15, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Itaru Kanno
  • Patent number: 6358329
    Abstract: The resist residue removal method removes resist residues caused at the time of formation of an aluminum wiring pattern on a semiconductor wafer. The method includes the steps of removal fluid processing, washing, and drying. The method involves forming an atmosphere within a chamber, which houses a semiconductor wafer having an exposed aluminum wiring pattern, by controlling gas flow into the chamber according to the processing step being performed. By the resist residue removal method, yield of a wiring pattern is improved by prevention of local etching of an aluminum wiring pattern, or by prevention of thinning of the aluminum wiring pattern.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: March 19, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Seiji Muranaka, Itaru Kanno