Abstract: In one embodiment, a processor comprises a fetch unit and a pick unit. The fetch unit is configured to fetch instructions for execution by the processor. The pick unit is configured to schedule instructions fetched by the fetch unit for execution in the processor. The pick unit is configured to inhibit scheduling a delayed control transfer instruction (DCTI) until a delay slot instruction of the DCTI is available for scheduling. For example, in some embodiments, the pick unit may inhibit scheduling until the delay slot instruction is written to an instruction buffer, until the delay slot instruction is fetched, etc.

Abstract: A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M.

Abstract: Various techniques for mitigating dependencies between groups of instructions are disclosed. In one embodiment, such dependencies include “evil twin” conditions, in which a first floating-point instruction has as a destination a first portion of a logical floating-point register (e.g., a single-precision write), and in which a second, subsequent floating-point instruction has as a source the first portion and a second portion of the same logical floating-point register (e.g., a double-precision read). The disclosed techniques may be applicable in a multithreaded processor implementing register renaming. In one embodiment, a processor may enter an operating mode in which detection of evil twin “producers” (e.g., single-precision writes) causes the instruction sequence to be modified to break potential dependencies. Modification of the instruction sequence may continue until one or more exit criteria are reached (e.g., committing a predetermined number of single-precision writes).

Abstract: A mechanism for handling unfused multiply-add accrued exception bits includes a processor including a floating point unit, a storage, and exception logic. The floating-point unit may be configured to execute an unfused multiply-accumulate instruction defined with the instruction set architecture (ISA). The unfused multiply-accumulate instruction may include a multiply sub-operation and an accumulate sub-operation. The storage may be configured to maintain floating-point exception state information. The exception logic may be configured to capture the floating-point exception state after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, for example, and to update the storage to reflect the floating-point exception state.

Abstract: A method and apparatus for rapidly severing a decoy towline extending from an aircraft by a mechanical spring actuated cutting blade and a thermal fuse type of release mechanism eliminating a pyrotechnic actuation device. The cutting blade is biased toward cutting engagement with the towline by a preloaded coil compression spring retained in the loaded position by a length of a polymer cord. The polymer cord has a heater wire wrapped about a portion of the cord which is connected to a DC voltage supply. The heater wire melts the cords when electrically connected to the DC power supply which releases the restraint on the spring which then drives the cutting blade into severing engagement with the towline.

Abstract: A system and method for precisely identifying an instruction causing a performance-related event is disclosed. The instruction may be detected while in a pipeline stage of a microprocessor preceding a writeback stage and the microprocessor's architectural state may not be updated until after information identifying the instruction is captured. The instruction may be flushed from the pipeline, along with other instructions from the same thread. A hardware trap may be taken when the instruction is detected and/or when an event counter overflows or is within a given range of overflowing. A software trap handler may capture and/or log information identifying the instruction, such as one or more extended address elements, before returning control and initiating a retry of the instruction. The captured and/or logged information may be stored in an event space database usable by a data space profiler to identify performance bottlenecks in the application containing the instruction.

Abstract: A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch.

Abstract: This invention is directed to a wastewater treatment system having a fluidizable media carrying anoxic bacteria in a first treatment zone and a filter membrane positioned in a second treatment zone. A wastewater is contacted with the fluidizable media and further contacted with air and a filter membrane.

Abstract: This invention is directed to a wastewater treatment system having a fluidizable media carrying anoxic bacteria in a first treatment zone and a filter membrane positioned in a second treatment zone. A wastewater is contacted with the fluidizable media and further contacted with air and a filter membrane.

Abstract: A container (210) for holding granular or powdered material and formed by a top wall (212), a bottom wall (214), a front wall (216), a rear wall (218), a first side wall (220), and a second side wall (222). A rotatably removable lid (D) is interiorly mounted with a scoop (32) and is pivotally hinged to a collar (300) that includes a sealing gasket (330). The collar (300) mounts to the walls of the container (210). A sealing wall 240 of the lid (D) cooperates with the gasket 300 to prevent the contents from spilling. The container (210) incorporates powder control features, a container wall junction (50) preferred geometry and congruent scoop (32) enabling convenient access to the contents, a tolerance variation accommodating and strength improving, J-shaped collar (300) and interlocking indentations (290) and flex clips (310), and a pressure controlling portion (350) that prevents unwanted deformation due to pressure differentials.

Abstract: A method and mechanism for monitoring events in a processing system. A performance monitoring mechanism includes is configured to store a count of events in an event counter. Periodically, the count stored in the event counter is updated to a new count. If the new count equals a predetermined value, an indication that the count equals the predetermined value is conveyed. If the new count does not equal the predetermined value, but is within a given epsilon of the predetermined value and the occurrence of a corresponding event is detected, an indication that the count equals the predetermined value is conveyed. The mechanism is further configured to suppress event counts which correspond to mis-speculations.

Abstract: A method and mechanism for controlling threads in a multithreaded multicore processor. A processor includes multiple cores, each of which are capable of executing multiple threads. A control register which is shared by each of the cores is utilized to control the status of the threads in the processing system. In one embodiment, the shared register includes a single bit for each thread in the processor. Depending upon the value written to a bit of the shared register, one of three results may occur with respect to a thread which corresponds to the bit. In one embodiment, writing a “0” to a bit of the shared register will cause a corresponding thread to be Parked. Writing a “1” to a bit of the shared register will cause a corresponding thread to either be UnParked or be Reset. Whether writing a “1” to a bit of the register causes the corresponding thread to be UnParked or Reset depends upon a state of the processor.

Abstract: A wastewater treatment system for treating wastewater by processes which include aeration. The system includes an influent conduit for delivery of wastewater to be processed and a treatment tank for processing of the wastewater. Also included is an air conduit for providing compressed air for aeration of the wastewater and a particle size regulation device disposed between the conduit and the tank, wherein the particle size regulation device regulates a size of particles present in the wastewater to provide particle size regulated wastewater. The system also includes at least one aeration jet having a nozzle diameter sized to allow the particle size regulated wastewater to pass through the nozzle.

Abstract: In one embodiment, a system comprises one or more registers configured to store a plurality of values that identify a virtual address space (collectively a tag), a translation lookaside buffer (TLB), and a control unit coupled to the TLB and the one or more registers. The control unit is configured to detect whether or not the tag has changed and in response to a change in the tag, map the changed tag to an identifier having fewer bits than the total number of bits in the tag, and provide the current identifier to the TLB. The TLB is configured to detect a hit/miss in response to the identifier. A similar method is also contemplated.

Abstract: A creation, editing, and display tool for complex diagrams may enable portions of the diagram to be updated without having to update the entire diagram. The tool may use a set of rules that define the positioning and layout of various elements and relationships between elements in the diagram. The update mechanism may enable the rules to be applied to a subset of the diagram and may not update some portions of the diagram, such as those elements outside the viewing area. In some embodiments, a background or low priority process may apply the rules to those portions not updated. The tool may be used for various diagrams, including sequence diagrams and other complex, highly restrained diagram types.

Abstract: A method of manufacturing a turbine blade includes (a) supporting a turbine blade internal core support at opposite ends such that radially inner and outer ends of the turbine blade remain open during casting; (b) casting the blade including the airfoil portion, wherein the radially outer edge of the airfoil portion is inclined relative to horizontal; (c) machining the radially outer edge of the airfoil portion to form a peripheral shoulder about a radially outer opening in the airfoil portion; and (d) seating a tip cap on the peripheral shoulder and fixing the tip cap to the airfoil portion of the blade.

Abstract: A spar for a sailing vessel comprises an elongated member which projects upwardly at an oblique angle from the centerline of the vessel deck and defines a longitudinal axis of rotation. The elongated member has a longitudinal slot for mounting the jib. The elongated member has a longitudinally extending aerodynamic surface defined by a quasi-elliptical shape with identical starboard tack and port tack leading edges symmetric about a plane through the rotational axis and the slot.

Abstract: A downdraft exhaust cutting and shuttle table mechanism includes a cutting area and a loading area, which includes first and second elongated, horizontally disposed cutting tables which are shuttled into and out of a cutting area which includes a material cutting assembly positioned therein, the shuttle table mechanism including horizontal and vertical table movement devices which are operative to move the first and second cutting tables forwards and backwards between the cutting area and a loading area generally adjacent thereto and a vertical table movement device operative to move the first and second cutting tables upwards and downwards, the vertical and horizontal table movement devices cooperating to move each of the first and second cutting tables from a loading position generally horizontally forwards into the cutting area for cutting of material mounted thereon then generally horizontally backwards into the loading area to a position generally underneath the other of the cutting tables which has been

Abstract: A lightning detection system (100) includes at least one lightning detector (101-103). The said lightning detector (101-103) includes at least one x-ray detector (110) for providing x-ray data responsive to x-rays received, and an electric field or magnetic field detector (115) for providing electric field or magnetic field data responsive to electric field or magnetic field received. At least one signal processor (122) is coupled to the x-ray detector and the electric field or magnetic field detector. The processor (122) determines whether lightning will strike or has struck proximate to the lightning detector(s) (101-103) based on the x-ray data and electric field or magnetic field data, and can provide a strike point indication having an accuracy of generally better than (100) m.