Abstract: A container (210) for holding granular or powdered material and formed by a top wall (212), a bottom wall (214), a front wall (216), a rear wall (218), a first side wall (220), and a second side wall (222). A rotatably removable lid (D) is interiorly mounted with a scoop (32) and is pivotally hinged to a collar (300) that includes a sealing gasket (330). The collar (300) mounts to the walls of the container (210). A sealing wall 240 of the lid (D) cooperates with the gasket 300 to prevent the contents from spilling. The container (210) incorporates powder control features, a container wall junction (50) preferred geometry and congruent scoop (32) enabling convenient access to the contents, a tolerance variation accommodating and strength improving, J-shaped collar (300) and interlocking indentations (290) and flex clips (310), and a pressure controlling portion (350) that prevents unwanted deformation due to pressure differentials.

Abstract: An apparatus and a method for sheathing a medical device, tool, instrument or probe (generally, probe) is provided. Among other aspects, a probe support jig capable of supporting the probe is provided, which includes a mechanical coupling for accepting a sheath on a sheath shell. In use, the sheath shell is coupled at one end thereof to the support jig and the probe is fed into the sheath, which is coupled to the sheath shell at another end thereof.

Abstract: A device, system, and method for defending a computer network are described. network communications are received by a traffic filter, which dynamically determines whether the communications include an anomaly (i.e., are “anomalous” communications), or whether the communications are normal, and do not include an anomaly. The traffic filter routes normal communications to the correct device within its network for servicing he service requested by the communications. The traffic filter routes any anomalous communications to a virtual space engine, which is configured to fake a requested service (e.g., to entice deployment of a malicious payload). Anomalous communications are analyzed using an analytical engine, which can dynamically develop rules for handling anomalous communications in-line, and the rules developed by the analytical engine can be employed by the traffic filter against future received communications.

Abstract: An automatic delivery system includes a conveyor including powered first rollers arranged in parallel with each other defining a spacing between sequential ones of the first rollers. Fixed second rollers or fixed members are each connected to and coaxially aligned with individual ones of the first rollers and sequentially separated by the first roller spacing. The second rollers are divisible into at least two groups, each defining a loading station. Each of the loading stations has a station positioning device including at least one extension rod extending through and horizontally displaceable within the spacing between sequential ones of the first and second rollers. The station positioning device displaces a container received on the powered first rollers into and out of the loading station. A computer controlling the system and the station positioning device includes data for components inserted into the container at the loading station of each group.

Abstract: A software version management system comprising a host driver and at least one software module. The host driver comprises migration means to start, stop and replace the software modules on a computer system in response to replacement actions.

Abstract: The disclosed embodiments provide a system that uses unused bits in a memory pointer. During operation, the system determines a set of address bits in a address space that will not be needed for addressing purposes during program operation. Subsequently, the system stores data associated with the memory pointer in this set of address bits. The system masks this set of address bits when using the memory pointer to access the memory address associated with the memory pointer. Storing additional data in unused pointer bits can reduce the number of memory accesses for a program and improve program performance and/or reliability.

Abstract: Techniques are disclosed relating to suspending execution of a processor thread while monitoring for a write to a specified memory location. An execution subsystem may be configured to perform a load instruction that causes the processor to retrieve data from a specified memory location and atomically begin monitoring for a write to the specified location. The load instruction may be a load-monitor instruction. The execution subsystem may be further configured to perform a wait instruction that causes the processor to suspend execution of a processor thread during at least a portion of an interval specified by the wait instruction and to resume execution of the processor thread at the end of the interval. The wait instruction may be a monitor-wait instruction. The processor may be further configured to resume execution of the processor thread in response to detecting a write to a memory location specified by a previous monitor instruction.

Abstract: A hybrid method and system of treating wastewater with reduced energy usage is disclosed. The treatment system has a sorption system, an anaerobic digester that digests or converts at least a portion of the solids or sludge from the sorption system, and an aerobic treatment tank that partially reduces oxygen demand of a portion of the sludge from the sorption tank.

Abstract: A user interface for displaying retail search results is disclosed. The system and methods allow users to search for a plurality of retail items while simultaneously viewing a plurality of search results for each of the plurality of retail items. This interface allows users to easily compare the search results for each retail item, and to purchase a plurality of retail items simultaneously. In one example of the present disclosure, users may enter a plurality of retail items into a shopping list. The system may then display multiple results for each item on the shopping list in a carousel-like user interface, so users may view a plurality of results for a plurality of items simultaneously.

Abstract: A computer program product for integrated key serving is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes using a smart card of two or more smart cards with a support element of two or more support elements to create an encryption key and storing the encryption key in an encrypted file that can only be decrypted by the smart card and the support element used to create the encryption key.

Abstract: Systems and methods for efficient thread arbitration in a threaded processor with dynamic resource allocation. A processor includes a resource shared by multiple threads. The resource includes entries which may be allocated for use by any thread. Control logic detects long latency instructions. Long latency instructions have a latency greater than a given threshold. One example is a load instruction that has a read-after-write (RAW) data dependency on a store instruction that misses a last-level data cache. The long latency instruction or an immediately younger instruction is selected for replay for an associated thread. A pipeline flush and replay for the associated thread begins with the selected instruction. Instructions younger than the long latency instruction are held at a given pipeline stage until the long latency instruction completes. During replay, this hold prevents resources from being allocated to the associated thread while the long latency instruction is being serviced.

Abstract: A processor including instruction support for large-operand instructions that use multiple register windows may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may also include an instruction execution unit that, during operation, receives instructions for execution from the instruction fetch unit and executes a large-operand instruction defined within the ISA, where execution of the large-operand instruction is dependent upon a plurality of registers arranged within a plurality of register windows. The processor may further include control circuitry (which may be included within the fetch unit, the execution unit, or elsewhere within the processor) that determines whether one or more of the register windows depended upon by the large-operand instruction are not present. In response to determining that one or more of these register windows are not present, the control circuitry causes them to be restored.

Abstract: A container (210) for holding granular or powdered material and formed by a top wall (212), a bottom wall (214), a front wall (216), a rear wall (218), a first side wall (220), and a second side wall (222). A rotatably removable lid (D) is interiorly mounted with a scoop (32) and is pivotally hinged to a collar (300) that includes a sealing gasket (330). The collar (300) mounts to the walls of the container (210). A sealing wall 240 of the lid (D) cooperates with the gasket 300 to prevent the contents from spilling. The container (210) incorporates powder control features, a container wall junction (50) preferred geometry and congruent scoop (32) enabling convenient access to the contents, a tolerance variation accommodating and strength improving, J-shaped collar (300) and interlocking indentations (290) and flex clips (310), and a pressure controlling portion (350) that prevents unwanted deformation due to pressure differentials.

Abstract: A device for treating a damaged tissue includes an expandable scaffold positionable in a portion of a luminal tissue structure of a mammal; and maintained via stent technology, wherein the scaffold is comprised of electrospun fibers composed of a biodegradable compound. The scaffold serves as a temporary template that allows the tissue to be rebuilt.

Abstract: A container (210) for holding granular or powdered material and formed by a top wall (212), a bottom wall (214), a front wall (216), a rear wall (218), a first side wall (220), and a second side wall (222). A rotatably removable lid (D) is interiorly mounted with a scoop (32) and is pivotally hinged to a collar (300) that includes a sealing gasket (330). The collar (300) mounts to the walls of the container (210). A sealing wall 240 of the lid (D) cooperates with the gasket 300 to prevent the contents from spilling. The container (210) incorporates powder control features, a container wall junction (50) preferred geometry and congruent scoop (32) enabling convenient access to the contents, a tolerance variation accommodating and strength improving, J-shaped collar (300) and interlocking indentations (290) and flex clips (310), and a pressure controlling portion (350) that prevents unwanted deformation due to pressure differentials.

Abstract: Various techniques for mitigating dependencies between groups of instructions are disclosed. In one embodiment, such dependencies include “evil twin” conditions, in which a first floating-point instruction has as a destination a first portion of a logical floating-point register (e.g., a single-precision write), and in which a second, subsequent floating-point instruction has as a source the first portion and a second portion of the same logical floating-point register (e.g., a double-precision read). The disclosed techniques may be applicable in a multithreaded processor implementing register renaming. In one embodiment, a processor may enter an operating mode in which detection of evil twin “producers” (e.g., single-precision writes) causes the instruction sequence to be modified to break potential dependencies. Modification of the instruction sequence may continue until one or more exit criteria are reached (e.g., committing a predetermined number of single-precision writes).

Abstract: In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file is protected by a second error protection scheme. A check circuit is coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed. The check circuit is configured to detect an error in the value responsive to the value and the check bits. Coupled to the check circuit, the control unit is configured to cause reexecution of the first instruction responsive to the error detected by the check circuit.

Abstract: A device for treating a cardiovascular condition includes an expandable scaffold positionable in a portion of a vasculature of a mammal; and maintained via stent technology, wherein the scaffold is comprised of electrospun fibers composed of a biodegradable compound. The biodegradable compound serves as a temporary template that allows the cardiovascular tissue to be rebuilt about the scaffold.

Abstract: A pallet washing apparatus and its associated methodology, wherein all of the pallets in a vertical stack of pallets are cleaned simultaneously, the stack being vertically expanded to provide a separation distance between each pallet, with each pallet then being delivered onto individual conveyors passing through washing, rinsing and drying stations, such that cleaning spray may be directed against all surfaces of each pallet, all of the pallets then being restacked for removal in a single stack.

Abstract: A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M.