Patents by Inventor J. Joseph

J. Joseph has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160093523
    Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
    Type: Application
    Filed: December 9, 2015
    Publication date: March 31, 2016
    Inventors: Mark D. JAFFE, Alvin J. JOSEPH, Qizhi LIU, Anthony K. STAMPER
  • Publication number: 20160094011
    Abstract: A pulsed UV laser assembly includes a partial reflector or beam splitter that divides each fundamental pulse into two sub-pulses and directs one sub-pulse to one end of a Bragg grating and the other pulse to the other end of the Bragg grating (or another Bragg grating) such that both sub-pulses are stretched and receive opposing (positive and negative) frequency chirps. The two stretched sub-pulses are combined to generate sum frequency light having a narrower bandwidth than could be obtained by second-harmonic generation directly from the fundamental. UV wavelengths may be generated directly from the sum frequency light or from a harmonic conversion scheme incorporating the sum frequency light. The UV laser may further incorporate other bandwidth reducing schemes. The pulsed UV laser may be used in an inspection or metrology system.
    Type: Application
    Filed: September 18, 2015
    Publication date: March 31, 2016
    Inventors: Yujun Deng, J. Joseph Armstrong, Yung-Ho Alex Chuang, Vladimir Dribinski, John Fielden
  • Patent number: 9298395
    Abstract: According to one embodiment a memory system includes a circuit card and a separable area array connector on the circuit card. The system also includes a memory device positioned on the circuit card, wherein the memory device is configured to communicate with a main processor of a computer system via the area array connector.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Paul W. Coteus, Shawn A. Hall, Hillery C. Hunter, Douglas J. Joseph, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Todd E. Takken
  • Publication number: 20160071925
    Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
    Type: Application
    Filed: September 8, 2014
    Publication date: March 10, 2016
    Inventors: Mark D. JAFFE, Alvin J. JOSEPH, Qizhi LIU, Anthony K. STAMPER
  • Publication number: 20160056606
    Abstract: An improved laser uses a pump laser with a wavelength near 1109 nm and a fundamental wavelength near 1171 nm to generate light at a wavelength between approximately 189 nm and approximately 200 nm, e.g. 193 nm. The laser mixes the 1109 nm pump wavelength with the 5th harmonic of the 1171 nm fundamental, which is at a wavelength of approximately 234.2 nm. By proper selection of non-linear media, such mixing can be achieved by nearly non-critical phase matching. This mixing results in high conversion efficiency, good stability, and high reliability.
    Type: Application
    Filed: March 13, 2014
    Publication date: February 25, 2016
    Applicant: KLA-Tencor Corporation
    Inventors: Yung-Ho Chuang, J. Joseph Armstrong, Justin Dianhuan Liou, Vladimir Dribinski, John Fielden
  • Publication number: 20160043203
    Abstract: Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 11, 2016
    Inventors: Deborah A. Alperstein, David L. Harame, Alvin J. Joseph, Qizhi Liu, Keith J. Machia, Christa R. Willets
  • Patent number: 9257324
    Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: February 9, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Alan B. Botula, Renata Camillo-Castillo, James S. Dunn, Jeffrey P. Gambino, Douglas B. Hershberger, Alvin J. Joseph, Robert M. Rassel, Mark E. Stidham
  • Publication number: 20160019890
    Abstract: This disclosure generally relates to a system, apparatus, and method for achieving a vehicle state-based hands free noise reduction feature. A noise reduction tool is provided for applying a noise reduction strategy on a sound input that uses machine learning to develop future noise reduction strategies, where the noise reduction strategies include analyzing vehicle operational state information and external information that are predicted to contribute to cabin noise and selecting noise reducing pre-filter options based on the analysis. The machine learning may further be supplemented by off-line training to generate a speech quality performance measure for the sound input that may be referenced by the noise reduction tool for further noise reduction strategies.
    Type: Application
    Filed: July 17, 2014
    Publication date: January 21, 2016
    Inventors: Scott Andrew Amman, Francois Charette, Anthony Dwayne Cooprider, Yuksel Gur, Paul J. Joseph Nicastri, Gintaras Vincent Puskorious
  • Publication number: 20160019904
    Abstract: This disclosure generally relates to a system, apparatus, and method for achieving an adaptive vehicle state-based hands free noise reduction feature. A noise reduction tool is provided for adaptively applying a noise reduction strategy on a sound input that uses feedback speech quality measures and machine learning to develop future noise reduction strategies, where the noise reduction strategies include analyzing vehicle operational state information and external information that are predicted to contribute to cabin noise and selecting noise reducing pre-filter options based on the analysis.
    Type: Application
    Filed: July 17, 2014
    Publication date: January 21, 2016
    Inventors: Francois Charette, Anthony Dwayne Cooprider, Paul J Joseph Nicastri, Yuksel Gur, Scott Andrew Amman, Gintaras Vincent Puskorius
  • Patent number: 9231087
    Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: January 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Benoit, James R. Elliott, Peter B. Gray, Alvin J. Joseph, Qizhi Liu, Christa R. Willets
  • Publication number: 20150373103
    Abstract: An embodiment of the present technique may in a method for generating a report related to the transferability of an application to a cloud computing environment. The method may include receiving data related to characteristics of the application. The method may include comparing, via a processor, the data received to predetermined dimensions related to the transferability of an application to a cloud computing environment to determine a comparison value indicating how close the data is to each dimension. The method may include generating, via the processor, a report based on the comparison.
    Type: Application
    Filed: January 31, 2013
    Publication date: December 24, 2015
    Inventors: Jacques Tessier, Darren E Brust, Sandro J Joseph Del-Re, Peter M Gaines, Jambey Clinkscales, Jack E Strukel, Chadd A Schwartz, Kevin Morgan
  • Publication number: 20150372446
    Abstract: A repetition rate (pulse) multiplier includes one or more beam splitters and prisms forming one or more ring cavities with different optical path lengths that delay parts of the energy of each pulse. A series of input laser pulses circulate in the ring cavities and part of the energy of each pulse leaves the system after traversing the shorter cavity path, while another part of the energy leaves the system after traversing the longer cavity path, and/or a combination of both cavity paths. By proper choice of the ring cavity optical path length, the repetition rate of an output series of laser pulses can be made to be a multiple of the input repetition rate. The relative energies of the output pulses can be controlled by choosing the transmission and reflection coefficients of the beam splitters. Some embodiments generate a time-averaged output beam profile that is substantially flat in one dimension.
    Type: Application
    Filed: January 14, 2015
    Publication date: December 24, 2015
    Inventors: Yung-Ho Alex Chuang, Xiaoxu Lu, Justin Dianhuan Liou, J. Joseph Armstrong, Yujun Deng, John Fielden
  • Publication number: 20150364895
    Abstract: A pulse multiplier includes a beam splitter and one or more mirrors. The beam splitter receives a series of input laser pulses and directs part of the energy of each pulse into a ring cavity. After circulating around the ring cavity, part of the pulse energy leaves the ring cavity through the beam splitter and part of the energy is recirculated. By selecting the ring cavity optical path length, the repetition rate of an output series of laser pulses can be made to be a multiple of the input repetition rate. The relative energies of the output pulses can be controlled by choosing the transmission and reflection coefficients of the beam splitter. This pulse multiplier can inexpensively reduce the peak power per pulse while increasing the number of pulses per second with minimal total power loss.
    Type: Application
    Filed: August 21, 2015
    Publication date: December 17, 2015
    Inventors: Yung-Ho Alex Chuang, Justin Dianhuan Liou, J. Joseph Armstrong, Yujun Deng
  • Patent number: 9214561
    Abstract: An integrated recessed thin body field effect transistor (FET) and methods of manufacture are disclosed. The method includes recessing a portion of a semiconductor material. The method further includes forming at least one gate structure within the recessed portion of the semiconductor material.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: December 15, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michel J. Abou-Khalil, Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, James A. Slinkman
  • Publication number: 20150354350
    Abstract: Systems and methods for controlling one or more downhole tools. A vibratory signal is produced by interaction between an actuation profile and a contact profile. In response to the vibratory signal, a controller actuates one or more downhole tools.
    Type: Application
    Filed: June 4, 2014
    Publication date: December 10, 2015
    Applicant: BAKER HUGHES INCORPORATED
    Inventors: Basil J. Joseph, Keven O'Connor
  • Patent number: 9209589
    Abstract: A laser system for semiconductor inspection includes a fiber-based fundamental light source for generating fundamental light that is then converted/mixed by a frequency conversion module to generate UV-DUV laser light. The fundamental light source includes a nonlinear chirp element (e.g., a Bragg grating or an electro-optic modulator) that adds a nonlinear chirp to the seed light laser system prior to amplification by the fiber amplifier(s) (e.g., doped fiber or Raman amplifiers). The nonlinear chirp includes an x2 or higher nonlinearity and is configured to compensates for the Self Phase Modulation (SPM) characteristics of the fiber-based amplifiers such that fundamental light is generated that has a spectral E95 bandwidth within five times that of the seed light. When multiple series-connected amplifiers are used, either a single nonlinear chirp element is provided before the amplifier string, or a chirp elements are included before each amplifier.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: December 8, 2015
    Assignee: KLA-Tencor Corporation
    Inventor: J. Joseph Armstrong
  • Publication number: 20150340273
    Abstract: Various methods include: forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region; ion implanting the silicon substrate to amorphize a portion of the silicon substrate; forming a set of trenches through the STI regions and into the underlying silicon substrate region; undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the at least partially amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate; and sealing the set of cavities.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Mark D. Jaffe, Alvin J. Joseph, Qizhi Liu, Anthony K. Stamper
  • Patent number: 9171121
    Abstract: A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Hanyi Ding, Alvin J. Joseph, Wayne H. Woods, Jr.
  • Publication number: 20150299893
    Abstract: A frequency-conversion crystal annealing process includes a first ramp-up period (e.g., increasing the crystal's temperature to a first set point in the range of 100° C. to 150° C. over about 2 hours), a first fixed temperature period (e.g., maintaining at the first set point for 10 to 20 hours), a second ramp-up period (e.g., increasing from the first set point to a second set point above 150° C. over about 1 hour or more), a second fixed period (e.g., maintaining at the second set point for 48 to 300 hours), and then a temperature ramp-down period (e.g., decreasing from the second set point to room temperature over about 3 hours). Transitions from the first and second fixed temperature periods are optionally determined by —OH bonds absorption levels that are measured using Fourier transform infrared spectroscopy, e.g., by monitoring the absorption of —OH bonds (including H2O) near 3580 cm?1 in the infra-red spectrum.
    Type: Application
    Filed: June 29, 2015
    Publication date: October 22, 2015
    Inventors: Vladimir Dribinski, Yung-Ho Alex Chuang, J. Joseph Armstrong
  • Patent number: 9165819
    Abstract: According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: October 20, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Alan B. Botula, Jeffrey E. Hanrahan, Mark D. Jaffe, Alvin J. Joseph, Dale W. Martin, Gerd Pfeiffer, James A. Slinkman