Abstract: An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems, the hardware modeling system having a network interface for communicating between the hardware modeling system and the host computer, a central processing unit for controlling operation of the hardware modeling system, a central timing unit for generating timing signals for use in the operation of the hardware modeling system including the generation of precision clocks, data formatting strobes and sample strobes, an internal pattern bus for transmission of read/write requests from the central processing unit in one operational mode and pattern sequences for stimulation of the hardware modeling element in a second operational mode, a pattern controller for controlling presentation and delivery of the pattern sequences to the pattern bus, a pattern memory connected to the pattern controller for storing stimul

Abstract: This invention is a method and apparatus for multiplication which enables two factors to be packed into the same size data word as the product. The invention partitions two N bit buses (210, 202) into a first set of M bits and a second set of L bits. In the preferred embodiment the first set of M bits is N/2 most significant bits and the second set of L bits in N/2 least significant bits. Thus N=M+L and M=L. A multiplier (220) multiplies the second sets of L bits of each of the N bit numbers. This results in a product having up to 2L bits. The invention forms an output word having a first set of L bits being the most significant L bits of the product and a second set of M bits being the first set of M bits of the first N bit data word. In the preferred embodiment, a multiplexer (221) selects between the full product of 2L bits and the packed word output. The product may be scaled prior to partitioning via a left shifter (224) which shifts the product a selected number of bit positions.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235).

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235).

Abstract: Data processor with a transparency detection data transfer controller. Transparency register stores transparency data. Source address controller calculates source addresses for recall of data to be transferred. A comparator compares recalled data to stored transparency data and indicates whether data to be transferred is to be written to memory. Destination address controller writes data to be transferred into memory at calculated destination addresses if the comparator indicates data to be transferred is to be written to memory. The recalled data is stored in a source register for comparison. In the preferred embodiment data is not written into memory if it matches the transparency data. The transparency register may store a multiple of the minimum amount of data to be transferred. The data to be transferred is organized into data words having a selected size. This selected size is an integral multiple of a minimum amount of data to be transferred.

Abstract: A data processor Huffman encodes a series of multibit signed digital numbers determining the needed data size by detecting the bit position of the greatest significant bit that differs from the most significant bit. Either a left most bit change detector (237) determines this bit position or a left most one detector (237) determines this bit position from the absolute value of the multibit signed digital number. A set of least significant bits equal in number to the data size are selected from the multibit signed digital number. The data processor formed the Huffman encoded signal by concatenating the data size and the selected least significant bits if the original multibit signed digital number was greater than or equal to zero, or by concatenating the data size with the sum of the selected bits and a multibit digital constant having a number of "1's" equal to the data size.

Abstract: A data processing apparatus which operates on instruction controlling plural processor actions. Each instruction includes a data unit section and an independent data transfer section. The data unit section includes a data operation field that indicates the type of arithmetic logic unit operation and six operand fields. The six operand fields include four source data register fields and two destination register fields. The data unit (110) includes a multiplication unit (220) and an arithmetic logic unit (230). The data unit (110) may include a barrel rotator (235) for one input of the arithmetic logic unit (230). The rotated data may be stored in the first destination register instead of the multiply result. The address unit (120) operations according to the data transfer operation field. This could be a load, a store or a register to register move. Operations may be conditional based upon conditions stored in a status register (210) set by a prior output of the arithmetic logic unit (230).

Abstract: A data processor with a transparency detection data transfer controller transfers data from a block of source addresses to a block of destination addresses. A transparency register stores transparency data. A comparator compares the recalled data to the stored transparency data and indicates whether the data to be transferred is to be written to the memory. The recalled data to be transferred is not to be written into the memory if it matches the transparency data. The transparency register may store a multiple of a multibit minimum amount of data to be transferred. The data to be transferred has a selected size which is an integral multiple of a minimum amount of data to be transferred. The comparator includes plural data comparators corresponding to each multibit minimum amount of data to be transferred.

Abstract: A data processing device includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, dimension values defining a block of addresses, guide table having guide table entries and a table pointer. Each guide table entry has an address value. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of a block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table.

Abstract: Each of the two alternately actualable clutches of a threading shaft includes a clutch disc keyed to the shaft, and positioned between two annular members. One of the members is rotated coaxially of the shaft by a driving gear, and the other is movable axially by the ball detents of a camming mechanism in one direction to grip the clutch disc frictionally between the annular members thereby to transmit the rotation of said driving gear to the shaft, and in the opposite direction to disengage the driving gear from the shaft.

Abstract: This invention decodes a continuous stream of Huffman encoded data, each datum having a size portion of a predetermined number of bits and a value portion of a variable number of bits. The invention extracts the size portion, determines the variable number of bits of the value portion and extracts this value portion. The decoding of this value portion differs depending upon the sign bit. If this sign bit is "1", then translation is required. A mask constant having a single "1" bit is rotated an amount equal to the size aligning this single "1" bit with the most significant bit of the value portion. This rotated mask is ANDed with the value portion. A zero result indicates no translation is needed. The translation, if needed, takes place by subtraction. The quantity 2.sup.N -1 is subtracted from the value portion, where N is the size. A mask generator (239) forms the quantity 2.sup.N -1 by forming a number of right justified "1's" equal to the size.

Abstract: A method of computing a mean squared error between a predetermined plural number of pairs of first and second values employs a data processing apparatus (71, 72, 73, 74) having data registers (200), an arithmetic logic unit (230), a flags register (211), a multiplication unit (220), a source of instructions and an instruction decoder (245, 246, 250). The arithmetic logic unit (230) forms a difference between pairs. A status detector determines whether the result is less than zero. The flags register (211) stores status bits indicating this detected status. The arithmetic logic unit (230) conditionally either adds the difference to zero if the status bit indicates the difference was not less than zero or subtracts the difference from zero if the status bit indicated the difference was less than zero. The multiplication unit (220) forms the square. The square is added to a running sum. In an alternative embodiment, the arithmetic logic unit can perform operations upon data in separate sections.

Abstract: An improved system for and method of connecting a hardware modeling element to the pin electronics circuitry of a hardware modeling system, with the improved system having circuitry and structures that will allow it to be connected to a hardware modeling system that is powered, circuitry to indicate to the pin electronics circuitry that the improved system is connected to it, circuitry to identify the hardware modeling element supported by the improved system to the hardware modeling system, circuitry to indicate to the hardware modeling system when the hardware modeling element is initialized so evaluation of it by the hardware modeling system can commence, circuitry to generate selectable supply voltages for the powering the hardware modeling element, and a hardware modeling element connector that will allow the connection of a family of hardware modeling elements to the same connector without the need to change the connector.

Abstract: An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems, the hardware modeling system having a network interface for communicating between the hardware modeling system and the host computer, a central processing unit for controlling operation of the hardware modeling system, a central timing unit for generating timing signals for use in the operation of the hardware modeling system including the generation of precision clocks, data formatting strobes and sample strobes, an internal pattern bus for transmission of read/write requests from the central processing unit in one operational mode and pattern sequences for stimulation of the hardware modeling element in a second operational mode, a pattern controller for controlling presentation and delivery of the pattern sequences to the pattern bus, a pattern memory connected to the pattern controller for storing stimul

Abstract: A method is provided for deinterlacing pixels in a video display system operable to display images as a plurality of pixels arranged in first and second fields of interlaced rows, at least one video component level quantified by a numerical video component value characterizing each pixel in an image with the video component levels for the pixels in the first and second fields being updated on alternate scans. A global mean video component value is computed from the video component values generated for a previous scan of at least one of the first and second fields. A global standard deviation is computed for the global mean. A local mean video component value is computed from the video component values generated for a plurality of pixels being updated as part of the current scan of the first field and defining a neighborhood of a pixel in the second field being deinterlaced. A local standard deviation is computed form the local mean video component value.

Abstract: A colorspace converter for use with image processing systems. The colorspace converter transforms digitized image data in one colorspace into image data in another colorspace, for use by a computer monitor. The colorspace converter uses look-up tables and other logic devices, and avoids the need for processor intervention. The look-up tables may be loaded for simple mapping, and extension look-up tables may be loaded for nonlinear extension transformations.

Abstract: A dimensionally heat-recoverable article carrying a heat curable adhesive coating on a surface thereof, the adhesive coating comprising (a) a mixture of substantially solid particles of a first reactive component with separate substantially solid particles of at least a second reactive component and (b) a water soluble polymeric binder having substantially no hydroxyl groups, the first and second reactive components being present in the adhesive coating as substantially unreacted separate particles capable of reacting together to effect curing when the article is heated to its heat recovery temperature.

Abstract: Water heating apparatus by flow of electric current through the water from a set, for example, of eight electrodes whose surface areas for current flow are proportional to the value of two raised to the eight exponents zero to seven, that is 1 to 128. This gives an area range of 1:256 which can be switched in binary digital manner automatically by solid state circuitry in response to a temperature window, electric current flow or other indicators. This gives automatic compensation for wide water conductivity ranges and flow rates without any moving parts to give a practical mass-produced industrial or domestic water heater.