Abstract: Compounds which bind to shiga-like toxins (SLT) associated with enteric E. coli infection, compositions including the compounds, methods for the neutralization of (SLT) in a patient, and methods for the diagnosis of enteric E. coli infection are disclosed. The compounds include a core molecule bound to a plurality of linker arms, which in turn are bound to a plurality of bridging moieties, which in turn are bound to two or three di- or tri-saccharide moieties. The di- or tri-saccharide moieties themselves are active in binding to the SLTs. The presence of a plurality of bridged dimers of the di- and tri-saccharides is responsible for the increased binding affinity of the compounds relative to the di- and tri-saccharides themselves. The compounds, when administered in a timely fashion to a patient suffering from enteric E. coli infection, inhibit progression of this infection into hemolytic uremic syndrome (HUS).

Abstract: A method for forming a sum of the absolute value of the difference between each pair of numbers of respective first and second sets of numbers. The method includes forming the difference between corresponding numbers of the first and second sets. This difference is either added to or subtracted from a running sum based upon its sign. This is repeated for all number pairs. Preferably, the initial subtraction sets a status bit in a flag register (211) which controls the selection of addition or subtraction. The conditional addition to or subtraction from the running sum may generate a carry-out representing the most significant bit of the running sum. This carry-out is preferably stored and later added to the running sum to recover the most significant overflow bits. This technique is preferably practiced using an arithmetic logic unit (230) that can be split into plural independent sections (301, 302, 303, 304).

Abstract: Infrared communications scheme for an infrared transmitting device having a light emitting diode (LED) ramps up the power of a carrier frequency signal applied to the LED in a given time interval to a given value. The carrier frequency signal is then frequency modulated with a data message for transmission by the LED. The power of a DC signal applied to the LED may then be ramped up in a given time interval to a given value before the carrier frequency signal is modulated with a data message. After transmission of the data message, the power of the carrier frequency signal applied to the LED is ramped down in a given time interval to a given value. The power of the DC signal applied to the LED is then ramped down in a given time interval to a given value.

Abstract: The three-dimensional structure of crystalline pertussis holotoxin (PT) has been determined by X-ray crystallography. Crystal structures have also been determined for complexes of pertussis toxin with molecules relevant to the biological activity of PT. These three-dimensional structures were analyzed to identify functional amino acids appropriate for modification to alter the biological properties of PT. Similar procedures may be used to predict amino acids which contribute to the toxicity of the holotoxin, to produce immunoprotective, genetically-detoxified analogs of pertussis toxin.

Abstract: A spectroscopic system for measuring content of a constituent in a sample of a natural product is provided. The spectroscopic system includes a source for electromagnetic (EM) radiation and an absorbance filter for filtering EM radiation received from the source, where the absorbance filter transmits EM radiation of predetermined wavelengths solely by the absorbance characteristics of the filter material.

Abstract: A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. A base address instruction executing on any one of the processors generates the base address corresponding to that processor.

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data.

Abstract: Conditional hardware branching employs zero overhead loop logic and writing to a loop count register within a program loop. The zero overhead loop logic includes a program counter (701), loop end registers (711, 712, 713), loop start registers (721, 722, 723), loop counter registers (731, 732, 733), comparators (715, 716, 717) and loop priority logic (725). Normally the program counter (701) is incremented each cycle. The comparators (715, 716, 717) compare the address stored in the program counter (701) with respective loop end registers (711, 712, 713). If the address in the program counter (701) equals a loop end address, loop priority logic (725) decrements the loop count register and loads the program counter with the loop start address in loop start register. Hardware looping involves loading a loop count register during program loop operation.

Abstract: An illuminating sign assembly includes a sign housing for receiving and supporting a sign, and a bulb located within the housing which automatically activates to illuminate the sign at night. A rechargeable battery is connected to the bulb for supplying an operating electrical current to the bulb. A solar cell is connected to the battery, and operates to convert light to electrical energy to be stored in the battery for discharge to the bulb.

Abstract: This invention is a technique for summing plural sections of a single data word. The technique uses a repeated process forming larger and larger partial sums. Initially the single data word is rotated one section. The original single data word and the rotated single data word are masked with a mask having "1's" and "0's" in alternate sections. The mask blocks alternate sections so that adjacent sections of the original data word may be summed on a whole data word basis without any overflow disrupting the partial products. The two masked data words are then summed. This sum results in half as many partial sums as before. Each of these larger partial sums now occupies two original sections of the data word. The process can be repeated for these large partial sums. In the preferred embodiment this technique is used with an arithmetic logic unit (230) capable of forming mixed arithmetic and Boolean combinations of three inputs having a barrel rotator (235) driving one input.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shifter could be a left barrel rotator with wrap around or a controllable left/right shifter. The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being a left shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result.

Abstract: This invention involves computing a mean squared error between a predetermined plural number of pairs of first and second values. A data processing apparatus (71, 72, 73, 74) has data registers (200), an arithmetic logic unit (230), a flags register (211), a multiplication unit (220), a source of instructions and an instruction decoder (245, 246, 250). The arithmetic logic unit (230) forms a difference between pairs. The flags register (211) stores status bits indicating whether the result is less than zero. The arithmetic logic unit (230) conditionally either adds the difference to zero if the status bit indicates the difference was not less than zero or subtracts the difference from zero if the status bit indicated the difference was less than zero. The multiplication unit (220) forms the square. The square is added to a running sum.

Abstract: This invention performs conditional operations and conditional branches based upon mixed conditions. The invention performs a first arithmetic/logical operation via an arithmetic logic unit (230). At least one status bit in a status register (210) is set based upon the results. This status bit could be a negative status bit, a carry out status bit, an overflow status bit or a zero status bit. In a first embodiment, the arithmetic logic unit (230) performs a second operation conditional upon a selected one of the status bits. The status bits are then set based upon the results of this second operation. A third operation, which could be an arithmetic logic unit operation, a memory load, memory store, a register to register move, a subroutine call, subroutine return or program branch, is conditional upon the selected status bit, thus performing upon the logical AND of the results of the first and second operations.

Abstract: The present invention describes a novel method and apparatus for sampling an input/output pin of an electronic device at high speeds, comprising the steps of: driving the device input/output pin through a series resistor with a middle voltage between the high and low voltages of the device; sampling and latching the voltage at the input/output pin; comparing the latched voltage at the device input/output pin with a high threshold voltage which is between the high voltage of the device and the middle voltage; comparing the latched voltage at the device input/output pin with a low threshold voltage which is between the low voltage of the device and the middle voltage; and using the results of the two comparisons to determine whether the device input/output pin is driving high, driving low, or in an input mode.

Abstract: A data processor includes both integer and floating point operation units and operates as a reduced instruction set computer (RISC). A modification of the normal load/store RISC operations includes within in its instruction set some instructions that permit floating point operations to be paired with load or store operations. These operations include: vector floating point add; vector multiply accumulate; vector floating point multiply; vector multiply subtract; vector reverse subtract; vector round floating point input; vector round integer input; and vector floating point subtract.

Abstract: A hardware interface generates and synchronizes precisely timed digital signals. The hardware interface receives data bits and associated timing information for application to a Hardware Modeling Element (HME). Preferably there are at least two modules, each including a clock generating circuit which has an input for receiving a master clock signal, a divider circuit for generating therefrom a plurality of evenly timed internal clock signals, wherein a first one of the internal clock signals rises at the same time as the master clock signal, and a phase adjusting circuit for receiving a feedback control signal for adjusting a phase delay in accordance with a sensed throughput delay. Each module also includes a timing multiplexer which receives the internal clock signals and each having a plurality of data channels, each having approximately the same throughput delay.

Abstract: This invention is a manner of control of the addresses of memory accesses. The data processing device of this invention includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, a number of guide table entries and a table pointer. The guide table includes guide table entries, each guide table entry having an address value and dimension values defining a block of addresses. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values.

Abstract: An arithmetic logic unit (230) may be divided into a plurality of independent sections (301, 302, 303, 340). A bit zero of carry status signal corresponding to each section that is stored in a flags register (211), which preferably includes more bits than the maximum number of sections of the arithmetic logic unit (230). New status signals may overwrite the previous status signals or rotate the stored bits and store the new status signals. A status register (210) stores a size indicator that determines the a number of sections of the arithmetic logic unit (230). A status detector has a zero detector (321, 322, 323, 324) for each elementary section (301, 302, 303, 304) of the arithmetic logic unit (230). When there are fewer than the maximum number of sections, these zero signals are ANDed (331, 332, 341). A multiplexer couples the carry-out of an elementary (311, 312, 313, 314) to the carry-in of an adjacent elementary section (301, 302, 303, 304) or not depending on the selected number of sections.

Abstract: A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal.