Abstract: A data input circuit including a first input register, a second input register, and a write driver connected to the second input register. The first and second input registers are preferably series-connected. In the preferred embodiment, a multiplexer selectively connects one of the first and second input registers to the write driver. The input circuit may be embodied in a memory device and in memory systems.

Abstract: A synchronous SRAM comprising an SRAM core having a memory array of a plurality of bytes, having a plurality of byte write drivers, having sense amplifiers, and having I/O buffers; a plurality of byte write registers respectively connected to the write drivers, the byte write registers selectively activating corresponding byte write drivers to input data into the memory array during a write operation; a plurality of data inputs organized into bytes; a byte write enable input; a plurality of byte write inputs; and byte write enable circuitry connecting the byte write inputs and the byte write enable input to the byte write registers and selectively causing individual bytes of the data inputs to be written into the SRAM core when a predetermined asserted logic level is present on the byte write enable input and also depending on the asserted logic level on the individual byte write inputs.

Abstract: A circuit for internally caching a memory device having a main memory is comprised of a cache memory of smaller size than the main memory for storing certain of the same data stored in the main memory. A tag memory is provided for mapping the information stored in the cache memory. A logic circuit is in communication with the main memory, the cache memory, and the tag memory for controlling the input of data thereto and output of data therefrom. The cache memory, tag memory, and logic circuit are carried internally in the memory device.

Abstract: A synchronous burst SRAM device comprising an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers; an address register for receiving addresses for the memory array in the SRAM core; a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register; an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register; three chip enable inputs for receiving chip enable signals; chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of (1) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean

Abstract: An expandable-set, tag, cache circuit for use with a data cache memory comprises a tag memory divided into a first set and a second set for storing, under a single address location, first and second tag fields representative of first and second data, respectively. The tag memory also stores first and second signals representative of which of the sets is the least recently used. A comparator is responsive to a tag field of an address representative of requested data as well as to a first tag field output from the tag memory for producing an output signal indicative of a match therebetween. A second comparator is responsive to the same tag field of the address and to a second tag field output from the tag memory for producing an output signal indicative of a match therebetween. A first logic gate is responsive to the first and second comparators for producing an output signal indicative of the availability of the requested data in the data cache memory.

Abstract: The present invention is directed to a logic circuit for controlling the read latency time of a memory circuit. The logic circuit includes a first circuit for producing a plurality of values derived from a read enable signal. Each of the values represents the read enable signal delayed by a predetermined period of time. The logic circuit also includes a second circuit for selecting one of the plurality of values in response to at least one control signal. The selected value enables a read operation of the memory circuit. A method for controlling the read latency time of a memory circuit is also presented.

Abstract: A synchronous burst SRAM device comprising an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers; an address register for receiving addresses for the memory array in the SRAM core; a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register; an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register; three chip enable inputs for receiving chip enable signals; chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of (1) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean

Abstract: The present invention is directed to a logic circuit for controlling the read latency time of a memory circuit. The logic circuit includes a first circuit for producing a plurality of values derived from a read enable signal. Each of the values represents the read enable signal delayed by a predetermined period of time. The logic circuit also includes a second circuit for selecting one of the plurality of values in response to at least one control signal. The selected value enables a read operation of the memory circuit. A method for controlling the read latency time of a memory circuit is also presented.

Abstract: A cache memory circuit for use in a cache memory system having a predetermined width is comprised of a memory array divided into a cache data memory portion and a tag memory portion. The proportion of the tag memory portion with respect to the cache data memory portion is the same as the proportion of the cache data memory portion to the width of the cache memory system. Support circuitry is provided for reading information into and out of both of the memory portions. A method for laying out such a cache memory circuit is also disclosed.

Abstract: A data input circuit including a first input register, a second input register, and a write driver connected to the second input register. The first and second input registers are preferably series-connected. In the preferred embodiment, a multiplexer selectively connects one of the first and second input registers to the write driver. The input circuit may be embodied in a memory device and in memory systems.

Abstract: A circuit for controlling the data transmissions among two devices capable transmitting information, via an output buffer, over a bus, so as to prevent bus contention, is comprised of a first device enabled circuit for generating a first device enabled signal indicative of whether one of the devices is enabled to transmit information. A second device enabled circuit generates a second device enabled signal indicative of whether the other of the devices is enabled to transmit information. A circuit, which is in communication with the first and second device enabled circuits, generates an output enable signal. The output enable signal is input to one of the devices to create a delay between the end of a transmission of information by one device and the beginning of a transmission by the other device.

Abstract: The present invention is directed to a logic circuit for controlling the read latency time of a memory circuit. The logic circuit includes a first circuit for producing a plurality of values derived from a read enable signal. Each of the values represents the read enable signal delayed by a predetermined period of time. The logic circuit also includes a second circuit for selecting one of the plurality of values in response to at least one control signal. The selected value enables a read operation of the memory circuit. A method for controlling the read latency time of a memory circuit is also presented.

Abstract: A synchronous SRAM module comprises first and second SRAM chips. Each SRAM chip has three chip enable inputs. A module enable and memory selection circuit is coupled to the two SRAM chips to perform the dual tasks of (1) selectively enabling or disabling both SRAM chips and (2) choosing either the first or second SRAM chips for access. The SRAM module can also be placed in a pipelining mode where external signals from a microprocessor are ignored to facilitate internal operation, such as burst reads. A synchronous burst SRAM device employed in the SRAM module is also described.

Abstract: The present invention is directed to a logic circuit for controlling the read latency time of a memory circuit. The logic circuit includes a first circuit for producing a plurality of values derived from a read enable signal. Each of the values represents the read enable signal delayed by a predetermined period of time. The logic circuit also includes a second circuit for selecting one of the plurality of values in response to at least one control signal. The selected value enables a read operation of the memory circuit. A method for controlling the read latency time of a memory circuit is also presented.

Abstract: A synchronous memory circuit having a memory array and a control circuit. The control circuit is responsive to a clock signal having a rising edge and a falling edge. The control circuit generates control signals for accessing the memory array at the rising edge and the falling edge of the clock signal. A read circuit is responsive to the control signals and generates read data signals indicative of data stored in the memory array. A write circuit is responsive to the control signals and stores data in the memory array.

Abstract: A data input circuit including a first input register, a second input register, and a write driver connected to the second input register. The first and second input registers are preferably series-connected. In the preferred embodiment, a multiplexer selectively connects one of the first and second input registers to the write driver. The input circuit may be embodied in a memory device and in memory systems.

Abstract: A cache memory circuit for use in a cache memory system having a predetermined width is comprised of a memory array divided into a cache data memory portion and a tag memory portion. The proportion of the tag memory portion with respect to the cache data memory portion is the same as the proportion of the cache data memory portion to the width of the cache memory system. Support circuitry is provided for reading information into and out of both of the memory portions. A method for laying out such a cache memory circuit is also disclosed.

Abstract: A device and method for generating a refresh signal for use in a dynamic memory having an array of memory cells organized according to addresses, the device including a refresh data memory array, a write driver circuit responsive to a refresh signal and timing information for writing at least a portion of the timing information in the refresh data memory array according to addresses corresponding to addresses used in the array of memory cells, a circuit for reading the written timing information from the refresh data memory array corresponding to certain of the addresses, and a logic circuit responsive to the present value of the timing information and said read timing information for producing said refresh signal indicative of when a refresh is required.

Abstract: A synchronous SRAM module comprises first and second SRAM chips. Each SRAM chip has three chip enable inputs. A module enable and memory selection circuit is coupled to the two SRAM chips to perform the dual tasks of (1) selectively enabling or disabling both SRAM chips and (2) choosing either the first or second SRAM chips for access. The SRAM module can also be placed in a pipelining mode where external signals from a microprocessor are ignored to facilitate internal operation, such as burst reads. A synchronous burst SRAM device employed in the SRAM module is also described.

Abstract: A circuit for controlling which set of a four-way set associated cache memory receives data for storage includes a memory array for storing six bits of information representative of the relative use of the four sets within the cache memory. Least recently used (LRU) update logic operates in conjunction with bit write drivers to generate and write the six bits of information to the memory array in a single access cycle. Replace logic reads the stored information from the memory means and produces output signals therefrom. The output signals are used to control into which of the four sets data is written. Error detection and fault tolerant embodiments are also disclosed as is a method of controlling which set of a four-way set associative cache memory receives data for storage.