Abstract: A circuit for controlling which set of a four-way set associated cache memory receives data for storage includes a memory array for storing six bits of information representative of the relative use of the four sets within the cache memory. Least recently used (LRU) update logic operates in conjunction with bit write drivers to generate and write the six bits of information to the memory array in a single access cycle. Replace logic reads the stored information from the memory means and produces output signals therefrom. The output signals are used to control into which of the four sets data is written. Error detection and fault tolerant embodiments are also disclosed as is a method of controlling which set of a four-way set associative cache memory receives data for storage.

Abstract: An expandable-set, tag, cache circuit for use with a data cache memory comprises a tag memory divided into a first set and a second set for storing, under a single address location, first and second tag fields representative of first and second data, respectively. The tag memory also stores first and second signals representative of which of the sets is the least recently used. A comparator is responsive to a tag field of an address representative of requested data as well as to a first tag field output from the tag memory for producing an output signal indicative of a match therebetween. A second comparator is responsive to the same tag field of the address and to a second tag field output from the tag memory for producing an output signal indicative of a match therebetween. A first logic gate is responsive to the first and second comparators for producing an output signal indicative of the availability of the requested data in the data cache memory.

Abstract: A circuit for internally caching a memory device having a main memory is comprised of a cache memory of smaller size than the main memory for storing certain of the same data stored in the main memory. A tag memory is provided for mapping the information stored in the cache memory. A logic circuit is in communication with the main memory, the cache memory, and the tag memory for controlling the input of data thereto and output of data therefrom. The cache memory, tag memory, and logic circuit are carried internally in the memory device.

Abstract: A synchronous burst SRAM device comprising an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers; an address register for receiving addresses for the memory array in the SRAM core; a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register; an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register; three chip enable inputs for receiving chip enable signals; chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of (1) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean

Abstract: A method of using non-data bits of the memory device as data bits is comprised of the steps of determining which bits in the memory device are nonfunctional and which bits are functional. If any of the data bits is nonfunctional, the second step of the method is to connect a non-data bit to a data bit line. The second step may be carried out while the memory device is being bonded to a lead frame or during the external routing of the output pads of the memory device on a printed circuit board. The method of the present invention may also be carried out by providing a plurality of fusible links between the memory cells of the memory device and the memory devices output pads. The fusible links may be opened in a manner so that each output pad is connected to a functional bit.