Patents by Inventor Jae-Hoon Jang
Jae-Hoon Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11975722Abstract: The present embodiments relate to a vehicle control device and method, and a vehicle system. The vehicle control device may include a determinator determining a road surface condition based on vehicle driving information and determining whether to brake a vehicle based on a result of determining the road surface condition and a vehicle controller controlling a braking device according to a result of determining whether to brake the vehicle by the determinator and controlling a steering device based on control of the braking device.Type: GrantFiled: October 27, 2021Date of Patent: May 7, 2024Assignee: HL MANDO CORPORATIONInventor: Jae Hoon Jang
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Publication number: 20240143703Abstract: Provided is an entertainment system including: a creator terminal configured to transmit creative work information; an administrator terminal configured to select valid creative work information among the creative work information received from the creator terminal; a server configured to generate audio-visual data based on the valid creative work information uploaded by the administrator terminal and generate an non-fungible token (NFT) that corresponds one-to-one with the audio-visual data; an investor terminal configured to exchange the NFT generated by the server with a predetermined electronic currency; and a predetermined metaverse platform configured to generate the predetermined electronic money.Type: ApplicationFiled: October 31, 2023Publication date: May 2, 2024Inventor: Jae Hoon JANG
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Publication number: 20230268017Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.Type: ApplicationFiled: May 2, 2023Publication date: August 24, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-Il SHIM, Jae-Hoon JANG, Donghyuk CHAE, Youngho LIM, Hansoo KIM, Jaehun JEONG
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Patent number: 11715537Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.Type: GrantFiled: December 3, 2021Date of Patent: August 1, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Il Shim, Jae-Hoon Jang, Donghyuk Chae, Youngho Lim, Hansoo Kim, Jaehun Jeong
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Publication number: 20230094795Abstract: Disclosed in a reel-to-reel surface press apparatus. The reel-to-reel surface press apparatus includes an uncoiler and a recoiler, both transferring a component in a reel-to-reel method, a press disposed between the uncoiler and the recoiler, comprising a press plate pressing the component, and having a plurality of reference holes at an equal pitch along an edge of the press plate, a feeder disposed at the rear of the uncoiler and moving the component, and a controller configured to control the component to be transferred based on at least any one of the plurality of reference holes.Type: ApplicationFiled: August 9, 2022Publication date: March 30, 2023Inventors: Yong Nam Kim, Jae Hoon Jang
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Patent number: 11411024Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.Type: GrantFiled: August 17, 2020Date of Patent: August 9, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Yun Lee, Jae-Hoon Jang, Jae-Duk Lee, Joon-Hee Lee, Young-Jin Jung
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Publication number: 20220135044Abstract: The present embodiments relate to a vehicle control device and method, and a vehicle system. The vehicle control device may include a determinator determining a road surface condition based on vehicle driving information and determining whether to brake a vehicle based on a result of determining the road surface condition and a vehicle controller controlling a braking device according to a result of determining whether to brake the vehicle by the determinator and controlling a steering device based on control of the braking device.Type: ApplicationFiled: October 27, 2021Publication date: May 5, 2022Inventor: Jae Hoon JANG
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Publication number: 20220093195Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.Type: ApplicationFiled: December 3, 2021Publication date: March 24, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-Il SHIM, Jae-Hoon JANG, Donghyuk CHAE, Youngho LIM, Hansoo KIM, Jaehun JEONG
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Patent number: 11233067Abstract: A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.Type: GrantFiled: June 11, 2020Date of Patent: January 25, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Moon Kyu Song, Ki Yoon Kang, Jae Hoon Jang
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Patent number: 11214845Abstract: The invention relates to a steel sheet for tool, and method for manufacturing thereof. An embodiment of the present invention is a steel sheet for a tool comprising 0.4 to 0.6 wt % of C, 0.05 to 0.5 wt % of Si, 0.1 to 1.5 wt % of Mn, 0.05 to 0.5 wt % of V, 0.1 to 2.0 wt % of at least of one or two components selected from the group comprising Ni, Cr, Mo, and combinations thereof, and the balance of Fe and inevitable impurities, with respect to 100 wt % of the total steel sheet, and provides a steel sheet for a tool of which the deviation of Rockwell hardness by the position in the width direction is within 5 HRC, and the ratio of those having a wave height in the longitudinal direction within 20 cm is 90% or more with respect to the wave height per 1 m of the steel sheet comprising the central portion in the longitudinal direction of the steel sheet for a tool.Type: GrantFiled: June 29, 2016Date of Patent: January 4, 2022Assignee: POSCOInventors: Kyong Su Park, Jae Hoon Jang
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Patent number: 11205951Abstract: A power conversion device comprises: a DC link capacitor charged with a DC power supplied from a power supply part; a fuse part, for breaking a current which is output from or supplied to the power supply part and has a first breaking magnitude or greater; a relay part which comprises a first relay for connecting a positive terminal of the fuse part to a positive terminal of the DC link capacitor and a second relay for connecting a negative terminal of the fuse part to a negative terminal of the DC link capacitor; an initial charge part, for charging the DC link capacitor by using DC power supplied from the power supply part; and a power conversion part for converting the direct-current power supplied from the power supply part into AC power when the DC link capacitor has been charged and supplying the alternating-current power to a load terminal.Type: GrantFiled: August 2, 2017Date of Patent: December 21, 2021Assignee: LSIS CO., LTD.Inventor: Jae-Hoon Jang
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Patent number: 11177274Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.Type: GrantFiled: November 1, 2018Date of Patent: November 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Min Hwang, Han-Soo Kim, Won-Seok Cho, Jae-Hoon Jang
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Publication number: 20210295895Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.Type: ApplicationFiled: June 8, 2021Publication date: September 23, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-Il Shim, Jae-Hoon Jang, Donghyuk Chae, Youngho Lim, Hansoo Kim, Jaehun Jeong
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Patent number: 11062784Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.Type: GrantFiled: April 9, 2020Date of Patent: July 13, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Il Shim, Jae-Hoon Jang, Donghyuk Chae, Youngho Lim, Hansoo Kim, Jaehun Jeong
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Patent number: 11031411Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.Type: GrantFiled: July 8, 2019Date of Patent: June 8, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hwan Son, Jae-Hoon Jang, Jee-Hoon Han
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Publication number: 20210152079Abstract: A power conversion device comprises: a DC link capacitor charged with a DC power supplied from a power supply part; a fuse part, for breaking a current which is output from or supplied to the power supply part and has a first breaking magnitude or greater; a relay part which comprises a first relay for connecting a positive terminal of the fuse part to a positive terminal of the DC link capacitor and a second relay for connecting a negative terminal of the fuse part to a negative terminal of the DC link capacitor; an initial charge part, for charging the DC link capacitor by using DC power supplied from the power supply part; and a power conversion part for converting the direct-current power supplied from the power supply part into AC power when the DC link capacitor has been charged and supplying the alternating-current power to a load terminal.Type: ApplicationFiled: August 2, 2017Publication date: May 20, 2021Inventor: Jae-Hoon JANG
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Patent number: 11004865Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.Type: GrantFiled: November 22, 2019Date of Patent: May 11, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang Soo Kim, Shin Hwan Kang, Jae Hoon Jang, Kohji Kanamori
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Patent number: 10978464Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.Type: GrantFiled: May 14, 2020Date of Patent: April 13, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hwan Son, Jae-Hoon Jang, Jee-Hoon Han
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Patent number: 10886289Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.Type: GrantFiled: April 5, 2018Date of Patent: January 5, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Shin-hwan Kang, Young-hwan Son, Dong-seog Eun, Chang-sup Lee, Jae-hoon Jang
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Patent number: RE50225Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.Type: GrantFiled: February 10, 2022Date of Patent: November 26, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Shin-Hwan Kang, Young-Hwan Son, Dong-seog Eun, Chang-sup Lee, Jae-hoon Jang