Patents by Inventor Jae-hyoung Choi

Jae-hyoung Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7179739
    Abstract: Embodiments of the present invention include methods of forming a contact to a capacitor in a semiconductor device. A metal silicide layer is formed at a top surface of a conductive plug of the semiconductor device that is coupled to a bottom electrode of the capacitor to provide an ohmic contact therebetween. Forming a metal silicide layer may include exposing a surface of the conductive plug, depositing a metal layer of the bottom electrode on the exposed surface of the conductive plug and thermally processing the semiconductor device to react a part of the deposited metal layer and the conductive plug to form the metal silicide layer. Methods of forming a semiconductor device including a capacitor having a metal silicide layer connecting a bottom electrode of the capacitor and a conductive plug are also provided.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: February 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Sik Choi, Jung-Hee Chung, Woo-Gwan Shim, Young-Sun Kim, Jae-Hyoung Choi, Se-Hoon Oh, Cha-Young Yoo
  • Patent number: 7172946
    Abstract: Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: February 6, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyoung Choi, Wan-don Kim, Cha-young Yoo, Suk-jin Chung
  • Publication number: 20070026625
    Abstract: In one embodiment, a method of fabricating a MIM capacitor includes forming an interlayer insulating layer having a contact plug on a semiconductor substrate, forming an etch stop layer on the interlayer insulating layer, and forming a mold layer having an opening exposing the contact plug on the etch stop layer. Next, a first conductive layer for the lower electrode is formed on the sidewalls and the bottom of the opening, and a photoresistive layer is formed on the first conductive layer. The mold layer and the photoresistive layer are then removed, and a composite dielectric layer is formed on the lower electrode. A second conductive layer is then formed on the composite dielectric layer. The composite dielectric layer may be composed of an oxide hafnium (HfO2) dielectric layer and an oxide aluminum (Al2O3) dielectric layer, with the oxide hafnium dielectric layer having a thickness of about 20 ? to about 50 ?.
    Type: Application
    Filed: July 28, 2006
    Publication date: February 1, 2007
    Inventors: Jung-Hee CHUNG, Jong-Cheol LEE, Jae-Hyoung CHOI, Jeong-Sik CHOI, Se-Hoon OH, Cha-Young YOO
  • Publication number: 20060244147
    Abstract: In a method of manufacturing a dielectric structure, after a tunnel oxide layer pattern is formed on a substrate, a floating gate is formed on the tunnel oxide layer. After a first dielectric layer pattern including a metal silicon oxide and a second dielectric layer pattern including a metal silicon oxynitride are formed, a control gate is formed on the dielectric structure. Since the dielectric structure includes at least one metal silicon oxide layer and at least one metal silicon oxynitride layer, the dielectric structure may have a high dielectric constant and a good thermal resistance. A non-volatile semiconductor memory device including the dielectric structure may have good electrical characteristics such as a large capacitance and a low leakage current.
    Type: Application
    Filed: January 25, 2006
    Publication date: November 2, 2006
    Inventors: Jong-Cheol Lee, Sung-Tae Kim, Young-Sun Kim, Cha-Young Yoo, Gab-Jin Nam, Young-Geun Park, Jae-Hyoung Choi, Jae-Hyun Yeo, Ha-Jin Lim, Yun-Seok Kim
  • Publication number: 20060216947
    Abstract: Provided are methods of manufacturing dielectric films including forming a first dielectric film on a wafer using atomic layer deposition (ALD) in a first batch type apparatus, forming a second dielectric film on the first dielectric film using atomic layer deposition in a second batch type apparatus, wherein the second dielectric film has a higher crystallization temperature than the first dielectric film and forming a third dielectric film on the second dielectric film using atomic layer deposition in a third batch type apparatus. Methods of manufacturing metal-insulator-metal (MIM) capacitors using the methods of forming the dielectric films and batch type atomic layer deposition apparatus for forming the dielectric films are also provided.
    Type: Application
    Filed: March 15, 2006
    Publication date: September 28, 2006
    Inventors: Jae-Hyoung Choi, Jung-hee Chung, Se-hoon Oh, Jong-cheol Lee
  • Publication number: 20060186452
    Abstract: Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer comprises a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, or a conductive metal oxynitride layer. The second conductive layer comprises a doped polysilicon germanium layer. The third conductive layer comprises a material having a lower resistance than that of the second conductive layer.
    Type: Application
    Filed: December 21, 2005
    Publication date: August 24, 2006
    Inventors: Gab-Jin Nam, Young-Sun Kim, Cha-Young Yoo, Jong-Cheol Lee, Jin-Tae Noh, Jae-Young Ahn, Young-Geun Park, Jae-Hyoung Choi, Jae-Hyun Yeo
  • Publication number: 20060166476
    Abstract: In a method of manufacturing a dielectric structure, after a first dielectric layer is formed on a substrate by using a metal oxide doped with silicon, the substrate is placed on a susceptor of a chamber. By treating the first dielectric layer with a plasma in controlling a voltage difference between the susceptor and a ground, a second dielectric layer is formed on the first dielectric layer. The second dielectric layer including a metal oxynitride doped with silicon having enough content of nitrogen is formed on the first dielectric layer. Therefore, dielectric properties of the dielectric structure comprising the first and the second dielectric layers can be improved and a leakage current can be greatly decreased. By adapting the dielectric structure to a gate insulation layer and/or to a dielectric layer of a capacitor or of a non-volatile semiconductor memory device, capacitances and electrical properties can be improved.
    Type: Application
    Filed: January 25, 2006
    Publication date: July 27, 2006
    Inventors: Jong-Cheol Lee, Sung-Tae Kim, Young-Sun Kim, Cha-Young Yoo, Gab-Jin Nam, Young-Geun Park, Jae-Hyoung Choi, Jae-Hyun Yeo, Ha-Jin Lim, Yun-Seok Kim
  • Publication number: 20060138523
    Abstract: Example embodiments of the present invention disclose a non-volatile semiconductor memory device, which may include a dielectric layer having an enhanced dielectric constant. A tunnel oxide layer pattern and a floating gate may be sequentially formed on a substrate. A dielectric layer pattern including metal oxide doped with Group III transition metals may be formed on the floating gate using a pulsed laser deposition process. The dielectric layer pattern having an increased dielectric constant may be formed of metal oxide doped with a transition metal such as scandium, yttrium, or lanthanum.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 29, 2006
    Inventors: Jong-Cheol Lee, Jae-Hyoung Choi, Han-Mei Choi, Gab-Jin Nam, Young-Sun Kim
  • Publication number: 20060113578
    Abstract: A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.
    Type: Application
    Filed: September 1, 2005
    Publication date: June 1, 2006
    Inventors: Eun-ae Chung, Jae-hyoung Choi, Jung-hee Chung, Young-sun Kim, Cha-young Yoo
  • Publication number: 20060046378
    Abstract: There are provided methods of fabricating a metal-insulator-metal (MIM) capacitor employing a metal nitride layer as a lower electrode. The method includes forming an insulating layer on a semiconductor substrate. A metal source gas and a nitride gas are supplied to the insulating layer, thereby depositing a metal nitride. A flushing gas including nitrogen is supplied to the metal nitride to enhance nitridation reaction. Along with the supply of a metal source gas and a nitride gas, the operation of supplying a flushing gas is performed at least one time alternately and repeatedly, thereby forming a metal nitride layer.
    Type: Application
    Filed: August 23, 2005
    Publication date: March 2, 2006
    Inventors: Jae-Hyoung Choi, Young-Sun Kim, Cha-Young Yoo, Jung-Hee Chung
  • Publication number: 20060046380
    Abstract: Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
    Type: Application
    Filed: August 24, 2005
    Publication date: March 2, 2006
    Inventors: Jae-hyoung Choi, Jung-hee Chung, Cha-young Yoo, Young-sun Kim, Se-hoon Oh
  • Patent number: 6995071
    Abstract: Methods of forming metal-insulator-metal type capacitors in integrated circuit memory devices can include crystallizing an HfO2 dielectric layer on a lower electrode of a capacitor structure in a low temperature plasma treatment at a temperature in range between about 250 degrees Centigrade and about 450 degrees Centigrade. An upper electrode can be formed on the HfO2 dielectric layer.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: February 7, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-hoon Oh, Jung-hee Chung, Jae-hyoung Choi, Jeong-sik Choi, Sung-tae Kim, Cha-young Yoo
  • Publication number: 20050227432
    Abstract: A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a meta-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.
    Type: Application
    Filed: April 1, 2005
    Publication date: October 13, 2005
    Inventors: Jae-hyoung Choi, Sung-tae Kim, Ki-chul Kim, Cha-young Yoo, Jeong-hee Chung, Se-hoon Oh, Jeong-sik Choi
  • Publication number: 20050059206
    Abstract: Integrated circuit devices are provided including an integrated circuit substrate and a capacitor on the integrated circuit substrate. The capacitor includes a lower electrode on the integrated circuit substrate, a dielectric layer on the lower electrode and an upper electrode on the dielectric layer. A barrier layer is provided between the dielectric layer and the upper electrode. The barrier layer includes titanium oxide. Related methods of fabricating integrated circuit devices are also provided.
    Type: Application
    Filed: March 18, 2004
    Publication date: March 17, 2005
    Inventors: Jung-hee Chung, Jae-hyoung Choi, Yun-jung Lee, Han-jin Lim
  • Publication number: 20050023640
    Abstract: A MIM capacitor can include a doped polysilicon contact plug in an interlayer insulating film. A lower electrode of the MIM capacitor includes a transition metal nitride film is on the doped polysilicon contact plug. A transition metal silicide film is between the doped polysilicon contact plug and the transition metal nitride film.
    Type: Application
    Filed: June 17, 2004
    Publication date: February 3, 2005
    Inventors: Jae-hyoung Choi, Jung-hee Chung, Cha-young Yoo, Nam-myun Cho, Jeong-sik Choi, Se-hoon Oh, Dong-kyun Park
  • Publication number: 20050020066
    Abstract: Embodiments of the present invention include methods of forming a contact to a capacitor in a semiconductor device. A metal silicide layer is formed at a top surface of a conductive plug of the semiconductor device that is coupled to a bottom electrode of the capacitor to provide an ohmic contact therebetween. Forming a metal silicide layer may include exposing a surface of the conductive plug, depositing a metal layer of the bottom electrode on the exposed surface of the conductive plug and thermally processing the semiconductor device to react a part of the deposited metal layer and the conductive plug to form the metal silicide layer. Methods of forming a semiconductor device including a capacitor having a metal silicide layer connecting a bottom electrode of the capacitor and a conductive plug are also provided.
    Type: Application
    Filed: June 8, 2004
    Publication date: January 27, 2005
    Inventors: Jeong-Sik Choi, Jung-Hee Chung, Woo-Gwan Shim, Young-Sun Kim, Jae-Hyoung Choi, Se-Hoon Oh, Cha-Young Yoo
  • Publication number: 20040248361
    Abstract: Methods of forming metal-insulator-metal type capacitors in integrated circuit memory devices can include crystallizing an HfO2 dielectric layer on a lower electrode of a capacitor structure in a low temperature plasma treatment at a temperature in range between about 250 degrees Centigrade and about 450 degrees Centigrade. An upper electrode can be formed on the HfO2 dielectric layer.
    Type: Application
    Filed: April 22, 2004
    Publication date: December 9, 2004
    Inventors: Se-hoon Oh, Jung-hee Chung, Jae-hyoung Choi, Jeong-sik Choi, Sung-tae Kim, Cha-young Yoo
  • Publication number: 20040219744
    Abstract: Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.
    Type: Application
    Filed: April 13, 2004
    Publication date: November 4, 2004
    Inventors: Se-Hoon Oh, Jung-Hee Chung, Jae-Hyoung Choi, Jeong-Sik Choi, Sung-Tae Kim, Cha-Young Yoo
  • Publication number: 20040102015
    Abstract: Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.
    Type: Application
    Filed: July 29, 2003
    Publication date: May 27, 2004
    Inventors: Jae-Hyoung Choi, Wan-Don Kim, Cha-Young Yoo, Suk-Jin Chung
  • Publication number: 20030224567
    Abstract: A fabrication method for forming a semiconductor device having a capacitor is provided. A capacitor dielectric layer is formed by depositing a first layer and a second layer. The second layer is a major portion of the capacitor dielectric layer. The first layer acts as a seed layer, while the second layer is expitaxially grown. The material of the second layer as deposited is partially crystal. Nuclear generation and crystal growth occur separately so that the crystalline characteristic of the capacitor dielectric layer and the capacitance characteristic of the capacitor are enhanced. Moreover, the capacitor dielectric layer is crystallized at a relatively low temperature or for a relatively short time, thereby reducing leakage current as well as reducing deformation in the lower electrode. Optionally, The material of the second layer as deposited is not partially crystal but amorphous.
    Type: Application
    Filed: November 12, 2002
    Publication date: December 4, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyoung Choi, Cha-Young Yoo, Suk-Jin Chung, Wan-Don Kim