Patents by Inventor Jae Il Kim

Jae Il Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Input apparatus and semiconductor memory apparatus having the input apparatus
    Patent number: 9564194
    Abstract: An input apparatus of a semiconductor memory may be provided. The input apparatus may include a first storage circuit configured to receive at least a portion of an input signal provided based on a pin reduction command which is enabled before an operation command through a pin and store the at least a portion of the input signal. The input apparatus may include a second storage circuit configured to receive a remaining portion of the input signal provided based on the operation command through the pin and store the remaining portion of the input signal. The input apparatus may include an arrangement circuit configured to control an output timing of the input signal stored in the first storage circuit and the second storage circuit.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: February 7, 2017
    Assignee: SK HYNIX INC.
    Inventors: Seung Geun Baek, Jae Il Kim
  • Semiconductor device and semiconductor system
    Patent number: 9559691
    Abstract: A semiconductor system may include a first semiconductor device configured to output a test stop signal and a calibration control signal. The semiconductor system may include a second semiconductor device configured to generate a first state code from an external resistor, a second state code from an internal resistor, and a third state code from a fuse array in response to the calibration control signal, and to select one of the first to third state codes as a selection code in response to the test stop signal and the calibration control signal.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 31, 2017
    Assignee: SK HYNIX INC.
    Inventor: Jae Il Kim
  • CLOCK GENERATION DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    Publication number: 20170017258
    Abstract: A clock generation device and a semiconductor device including the same are disclosed, which may tune an internal clock to a desired frequency. The clock generation device may include an oscillator configured to tune an oscillation signal in response to a tuning signal, and adjust a period of an internal clock. The clock generation device may include a counter configured to count the internal clock in response to a count enable signal, and output a count signal. The clock generation device may include a comparator configured to compare the count signal with a test count signal including a target count number of the internal clock, and output the tuning signal.
    Type: Application
    Filed: November 3, 2015
    Publication date: January 19, 2017
    Inventors: Min Su PARK, Jae Il KIM
  • Memory device with advanced refresh scheme
    Patent number: 9548099
    Abstract: A memory device includes a counter suitable for counting the number of times that a periodic wave is enabled and generating a code, one or more memory banks each including a plurality of word lines, and one or more measurement blocks corresponding to the memory banks, respectively, and suitable for measuring an active period of an activated word line in a corresponding memory bank among the memory banks, wherein each of the measurement blocks measures the active period of the activated word line based on a first value of the code at an activation starting point of the corresponding memory bank and a current value of the code.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: January 17, 2017
    Assignee: SK Hynix Inc.
    Inventors: No-Guen Joo, Jae-Il Kim
  • VIDEO ENCODING METHOD FOR ENCODING DIVISION BLOCK, VIDEO DECODING METHOD FOR DECODING DIVISION BLOCK, AND RECORDING MEDIUM FOR IMPLEMENTING THE SAME
    Publication number: 20170013281
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Application
    Filed: September 7, 2016
    Publication date: January 12, 2017
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, KOREAN BROADCASTING SYSTEM
    Inventors: Mun Churl KIM, Bum Shik LEE, Jae Il KIM, Chang Seob PARK, Sang Jin HAHM, In Joon CHO, Keun Sik LEE, Byung Sun KIM
  • MEDICAL IMAGING APPARATUS AND METHOD OF OPERATING SAME
    Publication number: 20170011509
    Abstract: Provided is a method of operating a medical imaging apparatus, comprising: acquiring a first image of a first type corresponding to a first respiratory state of an object; determining motion information of the object with respect to a respiratory state, based on first and second images of a second type respectively corresponding to the first respiratory state and a second respiratory state of the object; and generating a second image of the first type corresponding to the second respiratory state by applying the motion information to the first image of the first type.
    Type: Application
    Filed: June 1, 2016
    Publication date: January 12, 2017
    Applicant: Samsung Medison Co., Ltd.
    Inventors: Ji-won RYU, Jae-il KIM, Won-chul BANG, Young-taek OH, Kyong-joon LEE, Jung-woo CHANG, Ja-yeon JEONG
  • VIDEO ENCODING METHOD FOR ENCODING DIVISION BLOCK, VIDEO DECODING METHOD FOR DECODING DIVISION BLOCK, AND RECORDING MEDIUM FOR IMPLEMENTING THE SAME
    Publication number: 20160381359
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, KOREAN BROADCASTING SYSTEM
    Inventors: Mun Churl KIM, Bum Shik LEE, Jae Il KIM, Chang Seob PARK, Sang Jin HAHM, In Joon CHO, Keun Sik LEE, Byung Sun KIM
  • VIDEO ENCODING METHOD FOR ENCODING DIVISION BLOCK, VIDEO DECODING METHOD FOR DECODING DIVISION BLOCK, AND RECORDING MEDIUM FOR IMPLEMENTING THE SAME
    Publication number: 20160381357
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, KOREAN BROADCASTING SYSTEM
    Inventors: Mun Churl KIM, Bum Shik LEE, Jae Il KIM, Chang Seob PARK, Sang Jin HAHM, In Joon CHO, Keun Sik LEE, Byung Sun KIM
  • VIDEO ENCODING METHOD FOR ENCODING DIVISION BLOCK, VIDEO DECODING METHOD FOR DECODING DIVISION BLOCK, AND RECORDING MEDIUM FOR IMPLEMENTING THE SAME
    Publication number: 20160381358
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, KOREAN BROADCASTING SYSTEM
    Inventors: Mun Churl KIM, Bum Shik LEE, Jae Il KIM, Chang Seob PARK, Sang Jin HAHM, In Joon CHO, Keun Sik LEE, Byung Sun KIM
  • VIDEO ENCODING METHOD FOR ENCODING DIVISION BLOCK, VIDEO DECODING METHOD FOR DECODING DIVISION BLOCK, AND RECORDING MEDIUM FOR IMPLEMENTING THE SAME
    Publication number: 20160381360
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, KOREAN BROADCASTING SYSTEM
    Inventors: Mun Churl KIM, Bum Shik LEE, Jae Il KIM, Chang Seob PARK, Sang Jin HAHM, In Joon CHO, Keun Sik LEE, Byung Sun KIM
  • IMPEDANCE CALIBRATION CIRCUIT
    Publication number: 20160365855
    Abstract: An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first On Die Termination (ODT) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second ODT circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.
    Type: Application
    Filed: October 6, 2015
    Publication date: December 15, 2016
    Inventors: Seung Geun BAEK, Jae Il KIM
  • Semiconductor device having a secondary address generating unit for generating address signal in response to address signal from a first address generating unit
    Patent number: 9508410
    Abstract: A semiconductor device includes a control signal generating unit, a first address generating unit, and a second address generating unit. The control signal generating unit generates a read/write control signal and a selection control signal in response to an active signal. The first address generating unit generates a first address signal in response to the selection control signal and a second address signal. The second address generating unit generates the second address signal in response to the read/write control signal and the first address signal.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: November 29, 2016
    Assignee: SK HYNIX INC.
    Inventors: Seung Geun Baek, Jae Il Kim
  • Semiconductor integrated circuit with data latch control
    Patent number: 9502084
    Abstract: A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: November 22, 2016
    Assignee: SK HYNIX INC.
    Inventor: Jae Il Kim
  • Video encoding method for encoding division block, video decoding method for decoding division block, and recording medium for implementing the same
    Patent number: 9485512
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The coding unit (CU) blocks are divided into sub-CU blocks. The sub-CU blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of a CU block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: November 1, 2016
    Assignees: Korea Advanced Institute of Science and Technology, Korean Broadcasting System
    Inventors: Mun Churl Kim, Bum Shik Lee, Jae Il Kim, Chang Seob Park, Sang Jin Hahm, In Joon Cho, Keun Sik Lee, Byung Sun Kim
  • SEMICONDUCTOR SYSTEM AND METHOD FOR TESTING SEMICONDUCTOR DEVICE
    Publication number: 20160300626
    Abstract: A semiconductor device includes a plurality of first input pins; a parity check unit suitable for performing a parity check for command/address signals inputted to the plurality of first input pins, and determining the parity check result as a pass or fail; and one or more registers suitable for storing the inputted command/address signals when the parity check result is determined as the fail, wherein during a test operation, the number of signals having a first logic value among the command/address signals inputted to the plurality of first input pins does not correspond to the logic value of a parity bit.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 13, 2016
    Inventors: Sang-Ah HYUN, Jae-Il KIM
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20160293243
    Abstract: A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.
    Type: Application
    Filed: September 15, 2015
    Publication date: October 6, 2016
    Inventors: No-Guen JOO, Do-Hong KIM, Jae-Il KIM
  • COMPOSITION FOR TREATING OR PREVENTING ERECTILE DYSFUNCTION COMPRISING LDD175 AS ACTIVE INGREDIENT
    Publication number: 20160235710
    Abstract: The present invention relates to a pharmaceutical composition for treating or preventing erectile dysfunction, containing LDD175 as an active ingredient. Furthermore, the present invention relates to a co-administration preparation for treating or preventing erectile dysfunction, containing LDD175 and a PDE5 inhibitor as active ingredients. The LDD175 of the present invention has an excellent corporal smooth muscle relaxation effect, and thus significantly improved erectile function. Since the LDD175 of the present invention acts on BKCa channels, and thus is expected to have little adverse cardiovascular effects. The LDD175 of the present invention exhibits an erectile dysfunction therapeutic ability equivalent to that of udenafil, which is a PDE5 inhibitor, and showed a synergistic corporal smooth muscle relaxation effect when being co-administered with udenafil.
    Type: Application
    Filed: January 13, 2016
    Publication date: August 18, 2016
    Inventors: Sung Won LEE, Jong Kwan PARK, In Suk SO, Hyun Hwan SUNG, Jae Il KIM, Young Chul KIM, Jin Seok PARK
  • MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    Publication number: 20160232960
    Abstract: A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.
    Type: Application
    Filed: April 20, 2016
    Publication date: August 11, 2016
    Inventors: Sang-Ah HYUN, Jae-Il KIM
  • Semiconductor system and method for testing semiconductor device
    Patent number: 9390815
    Abstract: A semiconductor system includes a semiconductor device comprising: a plurality of first input pins suitable for receiving a plurality of command/address signals; a plurality of multi-purpose registers; and a parity check unit suitable for determining a parity check result as a pass when the number of first logic values in the command/address signals corresponds to a logic value of a parity bit, determining the parity check result as a fail when the number of the first logic values does not correspond to the logic value of the parity bit, and controlling the command/address signals to be stored in the multi-purpose registers; and a function test device suitable for applying the command/address signals to the first input pins during a function test, and controlling the command/address signals such that the number of the first logic values does not correspond to the logic value of the parity bit.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: July 12, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sang-Ah Hyun, Jae-Il Kim
  • Data strobing circuit and semiconductor apparatus using the same
    Patent number: 9390776
    Abstract: A data strobing circuit may include: an operating speed detection unit configured to detect an operating speed of a semiconductor apparatus according to a clock signal, and generate a control signal with a different value depending on the detected operating speed; and a strobe signal generation unit configured to adjust a delay time and pulse width of a read pulse according to the control signal and output an adjusted signal as a strobe signal.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: July 12, 2016
    Assignee: SK hynix Inc.
    Inventors: Seung Wook Oh, Jae Il Kim