Patents by Inventor Jae Il Kim

Jae Il Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160235710
    Abstract: The present invention relates to a pharmaceutical composition for treating or preventing erectile dysfunction, containing LDD175 as an active ingredient. Furthermore, the present invention relates to a co-administration preparation for treating or preventing erectile dysfunction, containing LDD175 and a PDE5 inhibitor as active ingredients. The LDD175 of the present invention has an excellent corporal smooth muscle relaxation effect, and thus significantly improved erectile function. Since the LDD175 of the present invention acts on BKCa channels, and thus is expected to have little adverse cardiovascular effects. The LDD175 of the present invention exhibits an erectile dysfunction therapeutic ability equivalent to that of udenafil, which is a PDE5 inhibitor, and showed a synergistic corporal smooth muscle relaxation effect when being co-administered with udenafil.
    Type: Application
    Filed: January 13, 2016
    Publication date: August 18, 2016
    Inventors: Sung Won LEE, Jong Kwan PARK, In Suk SO, Hyun Hwan SUNG, Jae Il KIM, Young Chul KIM, Jin Seok PARK
  • Publication number: 20160232960
    Abstract: A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.
    Type: Application
    Filed: April 20, 2016
    Publication date: August 11, 2016
    Inventors: Sang-Ah HYUN, Jae-Il KIM
  • Patent number: 9390815
    Abstract: A semiconductor system includes a semiconductor device comprising: a plurality of first input pins suitable for receiving a plurality of command/address signals; a plurality of multi-purpose registers; and a parity check unit suitable for determining a parity check result as a pass when the number of first logic values in the command/address signals corresponds to a logic value of a parity bit, determining the parity check result as a fail when the number of the first logic values does not correspond to the logic value of the parity bit, and controlling the command/address signals to be stored in the multi-purpose registers; and a function test device suitable for applying the command/address signals to the first input pins during a function test, and controlling the command/address signals such that the number of the first logic values does not correspond to the logic value of the parity bit.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: July 12, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sang-Ah Hyun, Jae-Il Kim
  • Patent number: 9390776
    Abstract: A data strobing circuit may include: an operating speed detection unit configured to detect an operating speed of a semiconductor apparatus according to a clock signal, and generate a control signal with a different value depending on the detected operating speed; and a strobe signal generation unit configured to adjust a delay time and pulse width of a read pulse according to the control signal and output an adjusted signal as a strobe signal.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: July 12, 2016
    Assignee: SK hynix Inc.
    Inventors: Seung Wook Oh, Jae Il Kim
  • Patent number: 9384807
    Abstract: A parameter setting circuit includes a first parameter setting unit configured to set a first parameter using first code signals generated by adjusting a value of parameter information to conform to a gear-down mode; a second parameter setting unit configured to generate pre-code signals by adjusting a value of the first code signals to conform to a specification of a second parameter, and set the second parameter using second code signals generated by adjusting a value of the pre-code signals according to a control signal; and a control section configured to generate the control signal according to whether it is the gear-down mode and whether the value of the first code signals is an odd number.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: July 5, 2016
    Assignee: SK HYNIX INC.
    Inventor: Jae Il Kim
  • Publication number: 20160180901
    Abstract: A data strobing circuit may include: an operating speed detection unit configured to detect an operating speed of a semiconductor apparatus according to a clock signal, and generate a control signal with a different value depending on the detected operating speed; and a strobe signal generation unit configured to adjust a delay time and pulse width of a read pulse according to the control signal and output an adjusted signal as a strobe signal.
    Type: Application
    Filed: February 19, 2015
    Publication date: June 23, 2016
    Inventors: Seung Wook OH, Jae Il KIM
  • Patent number: 9373374
    Abstract: A semiconductor apparatus may include a delay-locked loop configured to generate a delay-locked clock signal through a delay locking operation of an internal clock signal and an external clock signal, and delay an internal read command by a delay time tuned in the delay locking operation and generate a delay-locked internal command. The semiconductor apparatus may include a tuning control block configured to generate the internal read command in response to a self-tuning enable signal generated by determining a delay locking completion time of the delay-locked loop. The semiconductor apparatus may include a timing tuning block configured to generate delay control signals according to a phase difference of the delay-locked clock signal and the delay-locked internal command, and tune a delay time of the internal read command according to the delay control signals and generate a timing-tuned read command.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: June 21, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sang Ah Hyun, Jae Il Kim
  • Patent number: 9374096
    Abstract: A semiconductor apparatus includes a clock division block suitable for generating a first internal clock and a second internal clock having a first phase difference at which active sections of the first internal clock and the second internal clock overlap with each other by dividing a phase of a source clock at a predetermined rate, and a phase detection block suitable for outputting detection result information generated by combining a result obtained by detecting a phase of the first internal clock at a predetermined edge of a strobe signal and a result obtained by detecting a phase of the second internal clock at the predetermined edge of the strobe signal.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: June 21, 2016
    Assignee: SK Hynix Inc.
    Inventors: Ga-Ram Park, Jae-Il Kim
  • Patent number: 9349430
    Abstract: A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: May 24, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sang-Ah Hyun, Jae-Il Kim
  • Publication number: 20160118094
    Abstract: A semiconductor apparatus may include a delay-locked loop configured to generate a delay-locked clock signal through a delay locking operation of an internal clock signal and an external clock signal, and delay an internal read command by a delay time tuned in the delay locking operation and generate a delay-locked internal command. The semiconductor apparatus may include a tuning control block configured to generate the internal read command in response to a self-tuning enable signal generated by determining a delay locking completion time of the delay-locked loop. The semiconductor apparatus may include a timing tuning block configured to generate delay control signals according to a phase difference of the delay-locked clock signal and the delay-locked internal command, and tune a delay time of the internal read command according to the delay control signals and generate a timing-tuned read command.
    Type: Application
    Filed: January 28, 2015
    Publication date: April 28, 2016
    Inventors: Sang Ah HYUN, Jae Il KIM
  • Publication number: 20160111140
    Abstract: A semiconductor device includes a 1st controller suitable for generating refresh control signals for controlling two or more types of refresh operations according to an external refresh signal; and a 2nd controller suitable for controlling a plurality of word lines according to the refresh control signals such that the two or more types of refresh operations are alternately performed a predetermined number of times during a unit refresh period corresponding to the external refresh signal.
    Type: Application
    Filed: March 12, 2015
    Publication date: April 21, 2016
    Inventors: No-Guen JOO, Jae-Il KIM
  • Patent number: 9299399
    Abstract: The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data output portion receives an input control signal, a latch pulse signal, and a first output control signal. The data output portion receives an input clock signal in response to the input control signal and the latch pulse signal to generate a shift clock signal, and the data output portion also shifts the first output control signal in response to the shift clock signal to generate a second output control signal.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: March 29, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yu Ri Lim, Jae Il Kim
  • Patent number: 9300282
    Abstract: A semiconductor device includes a first pad suitable for receiving a first clock that is inputted from an exterior, a second pad suitable for receiving a second clock that is inputted from the exterior, a differential clock recognition unit suitable for recognizing between the first clock and the second clock as a positive clock of differential clocks and recognizing the other as a negative clock of the differential clocks in response to a mirror function signal which represents whether a mirror function is enabled or not, an output unit suitable for outputting an internal signal as an output signal in response to the differential clocks and controlling an output moment of the output signal in response to the mirror function signal and an output moment control signal, and a third pad suitable for supplying the output signal to the exterior.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 29, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yu-Ri Lim, Jae-Il Kim
  • Publication number: 20160078918
    Abstract: A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed to when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.
    Type: Application
    Filed: December 11, 2014
    Publication date: March 17, 2016
    Inventors: Sang-Ah HYUN, Jae-Il KIM
  • Publication number: 20160027483
    Abstract: A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal.
    Type: Application
    Filed: October 5, 2015
    Publication date: January 28, 2016
    Inventor: Jae Il KIM
  • Publication number: 20150380073
    Abstract: A memory device includes a counter suitable for counting the number of times that a periodic wave is enabled and generating a code, one or more memory banks each including a plurality of word lines, and one or more measurement blocks corresponding to the memory banks, respectively, and suitable for measuring an active period of an activated word line in a corresponding memory bank among the memory banks, wherein each of the measurement blocks measures the active period of the activated word line based on a first value of the code at an activation starting point of the corresponding memory bank and a current value of the code.
    Type: Application
    Filed: November 14, 2014
    Publication date: December 31, 2015
    Inventors: No-Guen JOO, Jae-Il KIM
  • Publication number: 20150349704
    Abstract: According to one embodiment of the present invention, a solar panel curtain device comprises: a solar panel provided tilting at a predetermined angle relative to the ground surface, corresponding to the angle of incidence of sunlight; a first roll housing provided at the lower edge of the solar panel, having formed therein a first rotational shaft and a solar panel curtain accommodating space, and having formed on one side thereof a slot adapted such that the solar panel curtain can withdraw into the inner accommodating space or advance out of the inner accommodating space; a second roll housing provided at the upper edge of the solar panel, and having formed therein a second rotational shaft; a first rail and a second rail respectively touching the two ends of the first rotational shaft and the two ends of the second rotational shaft, and performing rotational motions on two sides of the solar panel; and a panel curtain of which the ends on both sides respectively touch the first rail and the second rail, an
    Type: Application
    Filed: July 26, 2013
    Publication date: December 3, 2015
    Applicant: LIMITED PARTNERSHIP JUAN ENERGY
    Inventor: JAE IL KIM
  • Publication number: 20150332742
    Abstract: A semiconductor memory apparatus may include a data conversion control block configured to control the number of pipe input control signals and the number of pipe output control signals which are enabled, in response to a training control signal. The semiconductor memory apparatus may also include a data conversion block configured to receive parallel data and output serial data, in response to the pipe input control signals and the pipe output control signals.
    Type: Application
    Filed: September 17, 2014
    Publication date: November 19, 2015
    Inventor: Jae Il KIM
  • Patent number: 9190128
    Abstract: A semiconductor device includes a first buffer suitable for receiving and buffering data, a second buffer suitable for receiving and buffering a data strobe signal, a strobe line suitable for transferring the data strobe signal; a plurality of data transfer lines suitable for transferring data inputted at corresponding turns among data inputted in series through the first buffer, a latch signal generation block suitable for generating a plurality of latch signals which are sequentially activated, based on the data strobe signal transferred through the strobe line, a data latch block suitable for latching and aligning in parallel the data inputted in series through the first buffer, based on the latch signals, and a data transfer block suitable for transferring the data latched by the data latch block to the plurality of data transfer lines, according to a correspondence relationship determined based on an input start signal that is activated at a time when the input of data corresponding to the data input com
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: November 17, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ga-Ram Park, Jae-Il Kim
  • Patent number: 9191010
    Abstract: A semiconductor device includes a clock division block suitable for dividing a frequency of a source clock and generating first and second internal clocks; a strobe division block suitable for dividing a frequency of a strobe signal, and generating first and second internal strobe signals; and a phase difference detection block suitable for generating and alternately outputting first and second detection information as a detection result information.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: November 17, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ga-Ram Park, Jae-Il Kim