Patents by Inventor Jae Il Kim

Jae Il Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor devices and semiconductor systems
    Patent number: 10037788
    Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output commands and addresses. The first semiconductor device may be configured to output a strobe signal toggled and data after an initialization operation. The second semiconductor device may be configured to start the initialization operation if the commands have a first combination and stores internal data having a predetermined level during a set period of the initialization operation if the commands have a second combination.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 31, 2018
    Assignee: SK hynix Inc.
    Inventors: Jae Il Kim, Hong Jung Kim, Dae Suk Kim
  • Memory device and operating method thereof
    Patent number: 10020073
    Abstract: A memory device may include: a plurality of memory cells; at least one address storage unit; a fail detection unit suitable for comparing first and second read data that are read from at least one memory cell selected among the plurality of memory cells to detect a fail, and storing an address of the selected memory cell in the address storage unit when the fail is detected; and a refresh control unit suitable for refreshing the memory cell corresponding to the address stored in the address storage unit at a higher frequency than the other memory cells.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: July 10, 2018
    Assignee: SK Hynix Inc.
    Inventors: Tae-Kyun Kim, Jae-Il Kim, Hee-Seong Kim, Jun-Gi Choi
  • SEMICONDUCTOR DEVICE
    Publication number: 20180189134
    Abstract: A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal. The internal read signal generation circuit generates an internal read signal from a mask write signal in response to the delay selection signal and a clock. The internal write signal generation circuit delays the mask write signal by a predetermined delay period to generate an internal write signal.
    Type: Application
    Filed: July 3, 2017
    Publication date: July 5, 2018
    Inventors: Yong Mi KIM, Jae Il KIM
  • Comparing twice-read memory cell data for error detection in a memory device
    Patent number: 10014071
    Abstract: A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: July 3, 2018
    Assignee: SK Hynix Inc.
    Inventors: Min-Su Park, Jae-Il Kim, Tae-Kyun Kim, Jun-Gi Choi
  • Semiconductor devices
    Patent number: 10002651
    Abstract: A semiconductor device may include a valid command generation circuit and a training control circuit. The valid command generation circuit may be configured to latch an internal chip selection signal and an internal control signal in synchronization with a division clock signal to generate a latch chip selection signal and a latch control signal. The valid command generation circuit may be configured to generate a valid command for executing a predetermined function from the latch control signal. The training control circuit may be configured to generate a training result signal from the latch chip selection signal or the latch control signal based on a flag.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 19, 2018
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Dong Kyun Kim, Jae Il Kim
  • Impedance calibration circuit
    Patent number: 10003323
    Abstract: An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first On Die Termination (ODT) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second ODT circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 19, 2018
    Assignee: SK hynix Inc.
    Inventors: Seung Geun Baek, Jae Il Kim
  • SEMICONDUCTOR DEVICE
    Publication number: 20180166112
    Abstract: A semiconductor device may be provided. The semiconductor device may operate in a 2N mode as well as a normal mode.
    Type: Application
    Filed: August 2, 2017
    Publication date: June 14, 2018
    Applicant: SK hynix Inc.
    Inventors: Ki Hun KWON, Jae Il KIM
  • SEMICONDUCTOR DEVICES
    Publication number: 20180166110
    Abstract: A semiconductor device includes a flag signal generation circuit and a power-down signal generation circuit. The flag signal generation circuit generates a flag signal which is enabled in response to an operational frequency information signal. The power-down signal generation circuit generates a power-down signal for controlling input of a command in response to the flag signal and a clock enablement signal. A point of time that the power-down signal is generated is adjusted in response to the flag signal.
    Type: Application
    Filed: May 26, 2017
    Publication date: June 14, 2018
    Inventors: Sang Hyun KU, Jae Il KIM
  • Semiconductor devices
    Patent number: 9997222
    Abstract: A semiconductor device includes a flag signal generation circuit and a power-down signal generation circuit. The flag signal generation circuit generates a flag signal which is enabled in response to an operational frequency information signal. The power-down signal generation circuit generates a power-down signal for controlling input of a command in response to the flag signal and a clock enablement signal. A point of time that the power-down signal is generated is adjusted in response to the flag signal.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: June 12, 2018
    Assignee: SK HYNIX INC.
    Inventors: Sang Hyun Ku, Jae Il Kim
  • Breast cancer therapeutic agent containing 5'-hydroxy-5-nitro-indirubin-3'-oxime as active ingredient
    Publication number: 20180147182
    Abstract: A breast cancer therapeutic agent containing 5?-hydroxy-5-nitro-indirubin-3?-oxime as active ingredient has been disclosed. Further, a breast cancer therapeutic agent containing 5?-hydroxy-5-nitro-indirubin-3?-oxime as cyclin-dependent kinase (CDK) inhibitor, wherein said breast cancer is triple negative breast cancer (TNBC) and/or an estrogen receptor (ER) positive breast cancer including the tamoxifen-resistant estrogen receptor (ER) positive breast cancer has been disclosed.
    Type: Application
    Filed: May 15, 2017
    Publication date: May 31, 2018
    Inventors: Jae il KIM, Seon-Myung KIM, San Ho KIM, Moon Young PARK
  • VIDEO ENCODING METHOD FOR ENCODING DIVISION BLOCK, VIDEO DECODING METHOD FOR DECODING DIVISION BLOCK, AND RECORDING MEDIUM FOR IMPLEMENTING THE SAME
    Publication number: 20180124432
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 3, 2018
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, KOREAN BROADCASTING SYSTEM
    Inventors: Mun Churl KIM, Bum Shik LEE, Jae Il KIM, Chang Seob PARK, Sang Jin HAHM, In Joon CHO, Keun Sik LEE, Byung Sun KIM
  • SEMICONDUCTOR DEVICES
    Publication number: 20180102150
    Abstract: A semiconductor device may include a valid command generation circuit and a training control circuit. The valid command generation circuit may be configured to latch an internal chip selection signal and an internal control signal in synchronization with a division clock signal to generate a latch chip selection signal and a latch control signal. The valid command generation circuit may be configured to generate a valid command for executing a predetermined function from the latch control signal. The training control circuit may be configured to generate a training result signal from the latch chip selection signal or the latch control signal based on a flag.
    Type: Application
    Filed: May 31, 2017
    Publication date: April 12, 2018
    Applicant: SK hynix Inc.
    Inventors: Geun Ho CHOI, Dong Kyun KIM, Jae Il KIM
  • Semiconductor system and method for testing semiconductor device
    Patent number: 9941020
    Abstract: A semiconductor device includes a plurality of first input pins; a parity check unit suitable for performing a parity check for command/address signals inputted to the plurality of first input pins, and determining the parity check result as a pass or fail; and one or more registers suitable for storing the inputted command/address signals when the parity check result is determined as the fail, wherein during a test operation, the number of signals having a first logic value among the command/address signals inputted to the plurality of first input pins does not correspond to the logic value of a parity bit.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 10, 2018
    Assignee: SK Hynix Inc.
    Inventors: Sang-Ah Hyun, Jae-Il Kim
  • REFRESH CONTROL DEVICE
    Publication number: 20180090199
    Abstract: A refresh control device may include a first oscillator configured to generate a first oscillation signal, a second oscillator configured to generate a second oscillation signal having a different cycle from the first oscillation signal, a first address controller configured to latch an address in response to the first oscillation signal, and output the latched address when a refresh signal is enabled. The refresh control device may also include a second address controller configured to latch the address in response to the second oscillation signal, and output the latched address when the refresh signal is enabled. Further included may be a selector configured to select any one of the output of the first address controller and the output of the second address controller in response to a select signal, and output the selected output as a row hammer address.
    Type: Application
    Filed: April 25, 2017
    Publication date: March 29, 2018
    Applicant: SK hynix Inc.
    Inventors: Dae Suk KIM, Jae Il KIM
  • Refresh control device
    Patent number: 9928896
    Abstract: A refresh control device may include a first oscillator configured to generate a first oscillation signal, a second oscillator configured to generate a second oscillation signal having a different cycle from the first oscillation signal, a first address controller configured to latch an address in response to the first oscillation signal, and output the latched address when a refresh signal is enabled. The refresh control device may also include a second address controller configured to latch the address in response to the second oscillation signal, and output the latched address when the refresh signal is enabled. Further included may be a selector configured to select any one of the output of the first address controller and the output of the second address controller in response to a select signal, and output the selected output as a row hammer address.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 27, 2018
    Assignee: SK hynix Inc.
    Inventors: Dae Suk Kim, Jae Il Kim
  • Memory device
    Patent number: 9922728
    Abstract: A memory device may include a plurality of memory cells; and an error detection unit suitable for latching first read data of one or more memory cells selected from the plurality of memory cells after refreshing the selected memory cells, in a first phase, and suitable for detecting errors of the selected memory cells before refreshing the selected memory cells, in a second phase.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: March 20, 2018
    Assignee: SK Hynix Inc.
    Inventors: Min-Su Park, Jae-Il Kim
  • Semiconductor device which performs an active operation
    Patent number: 9911475
    Abstract: A semiconductor device includes an information signal conversion circuit suitable for generating a flag signal from an external control signal in response to an information signal, and an implicit precharge signal generation circuit suitable for generating an implicit precharge signal for performing a precharge operation between successive active operations, in response to the flag signal.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: March 6, 2018
    Assignee: SK hynix Inc.
    Inventors: Ki Hun Kwon, Jae Il Kim
  • SEMICONDUCTOR DEVICES, SEMICONDUCTOR SYSTEMS, AND METHODS THEREOF
    Publication number: 20180053567
    Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device outputs address signals. The first semiconductor device may receive or output data. The second semiconductor device may perform an impedance calibration operation and outputs pull-up codes and pull-down codes generated by the impedance calibration operation. The third semiconductor device may output internal data selected by the address signals as the data or store the data during a write operation or a read operation.
    Type: Application
    Filed: May 17, 2017
    Publication date: February 22, 2018
    Applicant: SK hynix Inc.
    Inventor: Jae Il KIM
  • SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS
    Publication number: 20180040355
    Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output commands and addresses. The first semiconductor device may be configured to output a strobe signal toggled and data after an initialization operation. The second semiconductor device may be configured to start the initialization operation if the commands have a first combination and stores internal data having a predetermined level during a set period of the initialization operation if the commands have a second combination.
    Type: Application
    Filed: June 16, 2017
    Publication date: February 8, 2018
    Applicant: SK hynix Inc.
    Inventors: Jae Il KIM, Hong Jung KIM, Dae Suk KIM
  • SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS
    Publication number: 20180040354
    Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a reset signal, command/address signals and data. The second semiconductor device may be configured to generate internal commands, internal addresses and internal data for performing an initialization operation. The second semiconductor device may be configured to store the internal data in a plurality of memory cells selected by the internal commands and the internal addresses.
    Type: Application
    Filed: June 16, 2017
    Publication date: February 8, 2018
    Applicant: SK hynix Inc.
    Inventors: Dae Suk KIM, Jae Il KIM, Hong Jung KIM