Patents by Inventor Jae Il Kim

Jae Il Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170054442
    Abstract: A semiconductor system may include a first semiconductor device configured to output a test stop signal and a calibration control signal. The semiconductor system may include a second semiconductor device configured to generate a first state code from an external resistor, a second state code from an internal resistor, and a third state code from a fuse array in response to the calibration control signal, and to select one of the first to third state codes as a selection code in response to the test stop signal and the calibration control signal.
    Type: Application
    Filed: October 29, 2015
    Publication date: February 23, 2017
    Inventor: Jae Il KIM
  • Publication number: 20170052840
    Abstract: A memory device may include: a plurality of memory cells; at least one address storage unit; a fail detection unit suitable for comparing first and second read data that are read from at least one memory cell selected among the plurality of memory cells to detect a fail, and storing an address of the selected memory cell in the address storage unit when the fail is detected; and a refresh control unit suitable for refreshing the memory cell corresponding to the address stored in the address storage unit at a higher frequency than the other memory cells.
    Type: Application
    Filed: March 2, 2016
    Publication date: February 23, 2017
    Inventors: Tae-Kyun KIM, Jae-Il KIM, Hee-Seong KIM, Jun-Gi CHOI
  • Publication number: 20170053715
    Abstract: Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time. The semiconductor device may include a repair detection unit configured to determine whether an inputted address is a repair address and output a repair detection signal. The semiconductor device may include a refresh control unit configured to simultaneously activate two or more word lines in response to a refresh command signal and sequentially activate the two or more word lines according to the repair detection signal.
    Type: Application
    Filed: November 5, 2015
    Publication date: February 23, 2017
    Inventors: Jae Il KIM, Seung Geun BAEK, Don Hyun CHOI
  • Patent number: 9576684
    Abstract: Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time. The semiconductor device may include a repair detection unit configured to determine whether an inputted address is a repair address and output a repair detection signal. The semiconductor device may include a refresh control unit configured to simultaneously activate two or more word lines in response to a refresh command signal and sequentially activate the two or more word lines according to the repair detection signal.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: February 21, 2017
    Assignee: SK HYNIX INC.
    Inventors: Jae Il Kim, Seung Geun Baek, Don Hyun Choi
  • Patent number: 9564194
    Abstract: An input apparatus of a semiconductor memory may be provided. The input apparatus may include a first storage circuit configured to receive at least a portion of an input signal provided based on a pin reduction command which is enabled before an operation command through a pin and store the at least a portion of the input signal. The input apparatus may include a second storage circuit configured to receive a remaining portion of the input signal provided based on the operation command through the pin and store the remaining portion of the input signal. The input apparatus may include an arrangement circuit configured to control an output timing of the input signal stored in the first storage circuit and the second storage circuit.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: February 7, 2017
    Assignee: SK HYNIX INC.
    Inventors: Seung Geun Baek, Jae Il Kim
  • Patent number: 9559691
    Abstract: A semiconductor system may include a first semiconductor device configured to output a test stop signal and a calibration control signal. The semiconductor system may include a second semiconductor device configured to generate a first state code from an external resistor, a second state code from an internal resistor, and a third state code from a fuse array in response to the calibration control signal, and to select one of the first to third state codes as a selection code in response to the test stop signal and the calibration control signal.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 31, 2017
    Assignee: SK HYNIX INC.
    Inventor: Jae Il Kim
  • Publication number: 20170017258
    Abstract: A clock generation device and a semiconductor device including the same are disclosed, which may tune an internal clock to a desired frequency. The clock generation device may include an oscillator configured to tune an oscillation signal in response to a tuning signal, and adjust a period of an internal clock. The clock generation device may include a counter configured to count the internal clock in response to a count enable signal, and output a count signal. The clock generation device may include a comparator configured to compare the count signal with a test count signal including a target count number of the internal clock, and output the tuning signal.
    Type: Application
    Filed: November 3, 2015
    Publication date: January 19, 2017
    Inventors: Min Su PARK, Jae Il KIM
  • Patent number: 9548099
    Abstract: A memory device includes a counter suitable for counting the number of times that a periodic wave is enabled and generating a code, one or more memory banks each including a plurality of word lines, and one or more measurement blocks corresponding to the memory banks, respectively, and suitable for measuring an active period of an activated word line in a corresponding memory bank among the memory banks, wherein each of the measurement blocks measures the active period of the activated word line based on a first value of the code at an activation starting point of the corresponding memory bank and a current value of the code.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: January 17, 2017
    Assignee: SK Hynix Inc.
    Inventors: No-Guen Joo, Jae-Il Kim
  • Publication number: 20170013281
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Application
    Filed: September 7, 2016
    Publication date: January 12, 2017
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, KOREAN BROADCASTING SYSTEM
    Inventors: Mun Churl KIM, Bum Shik LEE, Jae Il KIM, Chang Seob PARK, Sang Jin HAHM, In Joon CHO, Keun Sik LEE, Byung Sun KIM
  • Publication number: 20170011509
    Abstract: Provided is a method of operating a medical imaging apparatus, comprising: acquiring a first image of a first type corresponding to a first respiratory state of an object; determining motion information of the object with respect to a respiratory state, based on first and second images of a second type respectively corresponding to the first respiratory state and a second respiratory state of the object; and generating a second image of the first type corresponding to the second respiratory state by applying the motion information to the first image of the first type.
    Type: Application
    Filed: June 1, 2016
    Publication date: January 12, 2017
    Applicant: Samsung Medison Co., Ltd.
    Inventors: Ji-won RYU, Jae-il KIM, Won-chul BANG, Young-taek OH, Kyong-joon LEE, Jung-woo CHANG, Ja-yeon JEONG
  • Publication number: 20160381358
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, KOREAN BROADCASTING SYSTEM
    Inventors: Mun Churl KIM, Bum Shik LEE, Jae Il KIM, Chang Seob PARK, Sang Jin HAHM, In Joon CHO, Keun Sik LEE, Byung Sun KIM
  • Publication number: 20160381357
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, KOREAN BROADCASTING SYSTEM
    Inventors: Mun Churl KIM, Bum Shik LEE, Jae Il KIM, Chang Seob PARK, Sang Jin HAHM, In Joon CHO, Keun Sik LEE, Byung Sun KIM
  • Publication number: 20160381360
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, KOREAN BROADCASTING SYSTEM
    Inventors: Mun Churl KIM, Bum Shik LEE, Jae Il KIM, Chang Seob PARK, Sang Jin HAHM, In Joon CHO, Keun Sik LEE, Byung Sun KIM
  • Publication number: 20160381359
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, KOREAN BROADCASTING SYSTEM
    Inventors: Mun Churl KIM, Bum Shik LEE, Jae Il KIM, Chang Seob PARK, Sang Jin HAHM, In Joon CHO, Keun Sik LEE, Byung Sun KIM
  • Publication number: 20160365855
    Abstract: An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first On Die Termination (ODT) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second ODT circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.
    Type: Application
    Filed: October 6, 2015
    Publication date: December 15, 2016
    Inventors: Seung Geun BAEK, Jae Il KIM
  • Patent number: 9508410
    Abstract: A semiconductor device includes a control signal generating unit, a first address generating unit, and a second address generating unit. The control signal generating unit generates a read/write control signal and a selection control signal in response to an active signal. The first address generating unit generates a first address signal in response to the selection control signal and a second address signal. The second address generating unit generates the second address signal in response to the read/write control signal and the first address signal.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: November 29, 2016
    Assignee: SK HYNIX INC.
    Inventors: Seung Geun Baek, Jae Il Kim
  • Patent number: 9502084
    Abstract: A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: November 22, 2016
    Assignee: SK HYNIX INC.
    Inventor: Jae Il Kim
  • Patent number: 9485512
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The coding unit (CU) blocks are divided into sub-CU blocks. The sub-CU blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of a CU block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: November 1, 2016
    Assignees: Korea Advanced Institute of Science and Technology, Korean Broadcasting System
    Inventors: Mun Churl Kim, Bum Shik Lee, Jae Il Kim, Chang Seob Park, Sang Jin Hahm, In Joon Cho, Keun Sik Lee, Byung Sun Kim
  • Publication number: 20160300626
    Abstract: A semiconductor device includes a plurality of first input pins; a parity check unit suitable for performing a parity check for command/address signals inputted to the plurality of first input pins, and determining the parity check result as a pass or fail; and one or more registers suitable for storing the inputted command/address signals when the parity check result is determined as the fail, wherein during a test operation, the number of signals having a first logic value among the command/address signals inputted to the plurality of first input pins does not correspond to the logic value of a parity bit.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 13, 2016
    Inventors: Sang-Ah HYUN, Jae-Il KIM
  • Publication number: 20160293243
    Abstract: A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.
    Type: Application
    Filed: September 15, 2015
    Publication date: October 6, 2016
    Inventors: No-Guen JOO, Do-Hong KIM, Jae-Il KIM