Patents by Inventor Jae Il Kim

Jae Il Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150294699
    Abstract: The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data output portion receives an input control signal, a latch pulse signal, and a first output control signal. The data output portion receives an input clock signal in response to the input control signal and the latch pulse signal to generate a shift clock signal, and the data output portion also shifts the first output control signal in response to the shift clock signal to generate a second output control signal.
    Type: Application
    Filed: June 24, 2015
    Publication date: October 15, 2015
    Inventors: Yu Ri LIM, Jae Il KIM
  • Publication number: 20150294701
    Abstract: A semiconductor device includes a first buffer suitable for receiving and buffering data, a second buffer suitable for receiving and buffering a data strobe signal, a strobe line suitable for transferring the data strobe signal; a plurality of data transfer lines suitable for transferring data inputted at corresponding turns among data inputted in series through the first buffer, a latch signal generation block suitable for generating a plurality of latch signals which are sequentially activated, based on the data strobe signal transferred through the strobe line, a data latch block suitable for latching and aligning in parallel the data inputted in series through the first buffer, based on the latch signals, and a data transfer block suitable for transferring the data latched by the data latch block to the plurality of data transfer lines, according to a correspondence relationship determined based on an input start signal that is activated at a time when the input of data corresponding to the data input com
    Type: Application
    Filed: September 16, 2014
    Publication date: October 15, 2015
    Inventors: Ga-Ram PARK, Jae-Il KIM
  • Publication number: 20150256184
    Abstract: A semiconductor apparatus includes a clock division block suitable for generating a first internal dock and a second internal clock having a first phase difference at which active sections of the first internal clock and the second internal clock overlap with each other by dividing a phase of a source clock at a predetermined rate, and a phase detection block suitable for outputting detection result information generated by combining a result obtained by detecting a phase of the first internal clock at a predetermined edge of a strobe signal and a result obtained by detecting a phase of the second internal clock at the predetermined edge of the strobe signal.
    Type: Application
    Filed: July 28, 2014
    Publication date: September 10, 2015
    Inventors: Ga-Ram PARK, Jae-Il KIM
  • Publication number: 20150256183
    Abstract: A semiconductor device includes a dock division block suitable for dividing a frequency of a source clock and generating first and second internal clocks; a strobe division block suitable for dividing a frequency of a strobe signal, and generating first and second internal strobe signals; and a phase difference detection block suitable for generating and alternately outputting first and second detection information as a detection result information.
    Type: Application
    Filed: September 16, 2014
    Publication date: September 10, 2015
    Inventors: Ga-Ram PARK, Jae-Il KIM
  • Publication number: 20150227417
    Abstract: A semiconductor memory apparatus may include an error check and correction circuit block configured to receive a plurality of cell data, and output error-checked data and error data discrimination signals after receiving an error check enable signal; and a data bus inversion circuit block configured to receive the plurality of cell data, and output the plurality of cell data by inverting or non-inverting the cell data after receiving a read data bus inversion enable signal, the error check enable signal and the error data discrimination signals.
    Type: Application
    Filed: May 20, 2014
    Publication date: August 13, 2015
    Applicant: SK hynix Inc.
    Inventor: Jae Il KIM
  • Patent number: 9099170
    Abstract: The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data output portion receives an input control signal, a latch pulse signal, and a first output control signal. The data output portion receives an input clock signal in response to the input control signal and the latch pulse signal to generate a shift clock signal, and the data output portion also shifts the first output control signal in response to the shift clock signal to generate a second output control signal.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: August 4, 2015
    Assignee: SK Hynix Inc.
    Inventors: Yu Ri Lim, Jae Il Kim
  • Publication number: 20150187438
    Abstract: A semiconductor memory apparatus includes first data outputted from a first data storage region; second data outputted from a second data storage region; a data comparison block configured to perform a comparison to determine whether the first data and the second data are the same, and generate a comparison result signal; a timing control block configured to latch the comparison result signal in response to a clock and a latency signal, and output a comparison signal; and a data output block configured to receive a test signal and invert the first data in response to the comparison signal and output data.
    Type: Application
    Filed: April 9, 2014
    Publication date: July 2, 2015
    Applicant: SK hynix Inc.
    Inventors: Yu Ri LIM, Jae Il KIM
  • Publication number: 20150162071
    Abstract: A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address corresponding to a first external signal that is inputted at a random time, and a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation.
    Type: Application
    Filed: February 6, 2015
    Publication date: June 11, 2015
    Inventors: Seok-Cheol YOON, Bo-Yeun KIM, Jae-Il KIM, Kyoung-Chul JANG
  • Publication number: 20150155861
    Abstract: A semiconductor device includes a first pad suitable for receiving a first clock that is inputted from an exterior, a second pad suitable for receiving a second clock that is inputted from the exterior, a differential clock recognition unit suitable for recognizing between the first clock and the second clock as a positive clock of differential clocks and recognizing the other as a negative clock of the differential clocks in response to a mirror function signal which represents whether a mirror function is enabled or not, an output unit suitable for outputting an internal signal as an output signal in response to the differential clocks and controlling an output moment of the output signal in response to the mirror function signal and an output moment control signal, and a third pad suitable for supplying the output signal to the exterior.
    Type: Application
    Filed: May 23, 2014
    Publication date: June 4, 2015
    Applicant: SK hynix Inc.
    Inventors: Yu-Ri LIM, Jae-Il KIM
  • Publication number: 20150124535
    Abstract: A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 7, 2015
    Applicant: SK hynix Inc.
    Inventor: Jae Il KIM
  • Patent number: 9025397
    Abstract: A data write circuit of a semiconductor apparatus includes a data path configured to receive a pattern signal and generate a first delayed pattern signal; a data strobe signal path configured to receive the pattern signal and generate a second delayed pattern signal; a data latch block configured to latch the first delayed pattern signal in response to the second delayed pattern signal, and output a resultant signal; and a control block configured to generate the pattern signal, and vary a delay time of the data path according to a result of comparing phases of a latched signal of the data latch block and the pattern signal.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jae Il Kim
  • Patent number: 9013950
    Abstract: A column select signal generation circuit includes: a first current controller configured to control the level of a pre-column select signal in response to a bank active signal, a driver configured to generate an amplified column select signal in response to the pre-column select signal, and a second current controller configured to generate an output signal of the driver as a column select signal in response to the bank active signal.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: April 21, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jin Youp Cha, Jae Il Kim
  • Patent number: 9006349
    Abstract: The present invention relates to preparation and application of a temperature-sensitive polyethylene glycol/polyester block copolymer having a bioactive functional group introduced into a side chain thereof. More specifically, it relates to a temperature-sensitive polyethylene glycol/polyester block copolymer including a lactide segment having a bioactive functional group introduced into a side chain thereof and a method for preparing same. The temperature-sensitive polyethylene glycol/polyester block copolymer according to the present invention having a bioactive functional group introduced into a side chain thereof can be widely used as a drug delivery system, a support for tissue engineering, an adhesion inhibitor, etc.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: April 14, 2015
    Assignee: Ajou University Industry-Academic Cooperation Foundation
    Inventors: Moon Suk Kim, Jae Il Kim
  • Patent number: 9007852
    Abstract: A semiconductor integrated circuit includes: a latch unit configured to latch data in response to an input control signal; and a latch control unit configured to determine whether or not any one of first and second memory areas is successively accessed, and adjust timing of the input control signal.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jae Il Kim
  • Publication number: 20150043702
    Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.
    Type: Application
    Filed: September 23, 2014
    Publication date: February 12, 2015
    Inventors: Dae-Han KWON, Yong-Ju KIM, Jae-Il KIM, Taek-Sang SONG
  • Patent number: 8924679
    Abstract: A memory device includes a first bank group, a second bank group, where the first and second bank groups are each configured to output multi-bit data in parallel in response to a read command, a data transferor configured to receive the multi-bit data outputted in parallel from the first bank group or the second bank group and output the multi-bit data at a time interval corresponding to an operation mode, first global data buses configured to transfer the multi-bit data outputted from the first bank group to the data transferor, second global data buses configured to transfer the multi-bit data outputted from the second bank group to the data transferor, and a parallel-to-serial converter configured to convert the multi-bit data outputted from the data transferor into serial data according to the operation mode.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: December 30, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyoung-Jun Na, Jae-Il Kim
  • Patent number: 8908451
    Abstract: A data output circuit of a semiconductor device includes: a pattern data generation unit configured to generate pattern data in response to a bank selection signal, a variable delay unit configured to delay a source signal, which is generated in response to the bank selection signal, by a delay time corresponding to a delay control signal, a pattern control signal generation unit configured to generate a pattern control signal in response to an output signal of the variable delay unit, and a delay time control block configured to generate the delay control signal in response to the phases of the pattern control signal and the pattern data.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jae Il Kim
  • Patent number: 8908452
    Abstract: A semiconductor memory apparatus includes a data alignment control signal generation unit configured to output a data alignment control signal by generating a pulse when a tuning mode signal is enabled, and generate the data alignment control signal as a count pulse is inputted after the data alignment control signal generated by the tuning mode signal is outputted; a timing control block configured to determine a delay amount according to delay codes, generate a delay control signal by delaying the data alignment control signal, and output a timing control signal by latching the delay control signal at an enable timing of a data output control signal; a delay time control block configured to generate the delay codes; and a data alignment unit configured to convert parallel data into serial data, and change a data sequence of the serial data in response to the timing control signal.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jin Youp Cha, Jae Il Kim
  • Publication number: 20140347939
    Abstract: The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data output portion receives an input control signal, a latch pulse signal, and a first output control signal. The data output portion receives an input clock signal in response to the input control signal and the latch pulse signal to generate a shift clock signal, and the data output portion also shifts the first output control signal in response to the shift clock signal to generate a second output control signal.
    Type: Application
    Filed: September 13, 2013
    Publication date: November 27, 2014
    Applicant: SK hynix Inc.
    Inventors: Yu Ri LIM, Jae Il KIM
  • Publication number: 20140340968
    Abstract: A semiconductor integrated circuit includes: a latch unit configured to latch data in response to an input control signal; and a latch control unit configured to determine whether or not any one of first and second memory areas is successively accessed, and adjust timing of the input control signal.
    Type: Application
    Filed: September 5, 2013
    Publication date: November 20, 2014
    Applicant: SK hynix Inc.
    Inventor: Jae Il KIM