Abstract: A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit.

Abstract: An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided.

Abstract: Disclosed herein are a magnetometer which is capable of calculating an isotropic magnetic field component by use of three orthogonal coil sensors for magnetic field measurement and a method for measuring a magnetic field using the magnetometer, which records and displays the strength and/or direction of the magnetic field together with the measurement time and position of the magnetic field. The magnetometer can make a more comprehensive understanding of a magnetic field environment and to make a more accurate measurement of a magnetic field. In addition, the magnetometer can reduce time for measurement and result analysis, and obtain reliable measurement results.

Abstract: Asymmetrical SRAM cells are improved by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.

Abstract: Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell.

Abstract: Disclosed is a photosensitive resin composition suitable for use in a transflective liquid crystal display (LCD). The photosensitive resin composition uses, as an alkali-soluble binder resin, a blend of two kinds of binder resins. The first binder resin has a weight average molecular weight greater than or equal to 1,000 but lower than 20,000 and contains no reactive group. The second binder resin has a weight average molecular weight greater than or equal to 20,000 but lower than 80,000 and contains reactive groups. The photosensitive resin composition has good adhesion to an underlying substrate while forming a high resolution fine pattern.

Abstract: An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided.

Abstract: A heat-curable ink composition and a color filter produced using the ink composition are provided. The ink composition and the color filter are highly resistant to heat and chemicals due to the use of a polyester resin prepared by polycondensation. In addition, unreacted anhydride groups are removed using a monohydric alcohol in the preparation of the ink composition to make the ink composition and the color filter very stable during storage.

Abstract: In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line (WBL) are decoupled, RBL and WBL can be accessed simultaneously. Hence, the WRITE in the n-th cycle can be delayed to the n+1-th cycle as far as there is no data hazard such as reading data from memory before correct data are actually written to memory. As a result, there is no bandwidth loss, although the latency of the WRITE operation increases. WRITE stability issues in previous configurations with decoupled RBL and WBL are thus addressed.

Abstract: Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.

Abstract: Disclosed are a method and a system that adaptively transform visual contents inputted from a network, in accordance with the visual characteristics of a terminal user. A visual characteristics descriptor that describes the information of the user visual characteristics in a predetermined format is proposed. The descriptor includes the information of the color vision deficiency type and the color vision deficiency degree. The color vision deficiency may be described in numerical degree or textual degree. The invention adaptively transforms visual contents differently in accordance with the color vision deficiency type.

Abstract: This invention is concerned with a transmission control method and apparatus in a collision interval for a collision of multidimensional hopping patterns. In the present invention, each orthogonal wireless resource in the coordinate of the multidimensional orthogonal resource can hop according to the hopping pattern negotiated between a transmitter and a receiver, and each corresponding channel is distinguished by the hopping pattern. A specific multidimensional hopping pattern is allocated to each secondary station. The hopping pattern is either permanently allocated to the secondary stations or temporarily allocated from the primary station during a call set-up. The permanent allocation of the hopping pattern to the secondary stations is achieved when the hopping pattern is identified based on a unique identifier, such as ESN of the secondary station.

Abstract: The present invention relates to a method for manufacturing a color filter and a color filter manufactured by using the same. More particularly, the present invention pertains to a method for manufacturing a color filter, which includes performing plasma treatment of a black matrix (BM) pattern formed on a substrate to increase a difference in ink repellency of the black matrix pattern and a pixel unit, and a color filter manufactured by using the same. When the production method of the present invention is used, it is possible to provide the color filter in which color mixing does not occur in a pixel unit or between pixel units during discharging of ink by using an inkjet printing process, discoloration due to unfilling does not occur, a surface is uniform, and there is an insignificant step in the pixel unit or between the pixel units.

Abstract: The present invention relates to a composition for preparing a curable resin, comprising a) a compound represented by Formula 1; b) glycidyl (meth)acrylate; c) acid monoanhydride; and d) a solvent, a curable resin manufactured by the composition, and an ink composition comprising the same. The curable resin has a low viscosity and excellent flow properties, and the ink composition is excellent in terms of storage stability, heat resistance and chemical resistance.

Abstract: A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit.

Abstract: A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch.

Abstract: A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals.

Abstract: An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided.

Abstract: A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit.

Abstract: A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch.