Patents by Inventor Jae-Seung Hwang
Jae-Seung Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8728882Abstract: A manufacturing method for a thin film transistor array panel includes: providing a gate line including a gate electrode, on a substrate; providing a gate insulating layer covering the gate line; providing a semiconductor material layer on the gate insulating layer; providing a data wire material layer on the semiconductor material layer; providing a first photosensitive film pattern on the data wire material layer; etching the data wire material layer by using the first photosensitive film pattern as a mask; providing a second photosensitive film pattern by etching back the first photosensitive film pattern; etching the semiconductor material layer by using the second photosensitive film pattern as a mask; and etching the data wire material layer by using the second photosensitive film pattern as a mask to form a source electrode and a drain electrode. The etching the semiconductor material layer uses a first non-sulfur fluorinated gas.Type: GrantFiled: August 8, 2012Date of Patent: May 20, 2014Assignee: Samsung Display Co., Ltd.Inventors: Jae Seung Hwang, Jae-Won Lee, Jun Seo
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Publication number: 20130260568Abstract: A manufacturing method for a thin film transistor array panel includes: providing a gate line including a gate electrode, on a substrate; providing a gate insulating layer covering the gate line; providing a semiconductor material layer on the gate insulating layer; providing a data wire material layer on the semiconductor material layer; providing a first photosensitive film pattern on the data wire material layer; etching the data wire material layer by using the first photosensitive film pattern as a mask; providing a second photosensitive film pattern by etching back the first photosensitive film pattern; etching the semiconductor material layer by using the second photosensitive film pattern as a mask; and etching the data wire material layer by using the second photosensitive film pattern as a mask to form a source electrode and a drain electrode. The etching the semiconductor material layer uses a first non-sulfur fluorinated gas.Type: ApplicationFiled: August 8, 2012Publication date: October 3, 2013Applicant: SAMSUNG DISPLAY CO., LTD.Inventors: Jae Seung HWANG, Jae-Won LEE, Jun SEO
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Patent number: 8361849Abstract: A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.Type: GrantFiled: July 15, 2011Date of Patent: January 29, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hwan Ryu, Jun Seo, Eun-Young Kang, Jae-Seung Hwang, Sung-Un Kwon
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Patent number: 8241512Abstract: A method of forming an ion implantation mask includes forming a field area on a semiconductor substrate, forming an amorphous carbon layer on the semiconductor substrate, forming a hard mask layer on the amorphous carbon layer, forming an etching mask pattern on the hard mask layer, and etching the hard mask layer and the amorphous carbon layer to expose the field area through the etching mask pattern, wherein etching the hard mask layer and the amorphous carbon layer forms a hard mask layer pattern and an amorphous carbon layer pattern.Type: GrantFiled: October 31, 2008Date of Patent: August 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Woo Lee, Young-Mi Lee, Min-Chul Chae, Dae-Joung Kim, Jae-Seung Hwang
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Patent number: 8216944Abstract: Methods of forming patterns in semiconductor devices are provided including forming first patterns spaced apart from one another on an object structure. A first sacrificial layer is formed conformally on the first patterns and the object structure. A second pattern is formed on a sidewall of the first sacrificial layer, the second pattern having a height smaller than that of the first pattern from an upper surface of the object structure. The first patterns are selectively removed to form an opening that exposes the object structure. A third pattern is formed on a sidewall of the opening.Type: GrantFiled: March 2, 2010Date of Patent: July 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hyun Kwon, Jun Seo, Jae-Seung Hwang, Ji-Young Lee
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Patent number: 8158445Abstract: Methods of forming pattern structures and methods of manufacturing memory devices using the same are provided, the methods of forming pattern structures include forming an etching object layer on a substrate and performing a plasma reactive etching process on the etching object layer using an etching gas including at least ammonia (NH3) gas. The etching object layer includes a magnetic material or a phase change material.Type: GrantFiled: November 5, 2010Date of Patent: April 17, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hwan Ryu, Jae-Seung Hwang, Sung-Un Kwon, Kyoung-Ha Eom
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Publication number: 20110281428Abstract: A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.Type: ApplicationFiled: July 15, 2011Publication date: November 17, 2011Inventors: Yong-Hwan Ryu, Jun Seo, Eun-Young Kang, Jae-Seung Hwang, Sung-Un Kwon
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Patent number: 7989279Abstract: A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.Type: GrantFiled: June 10, 2008Date of Patent: August 2, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hwan Ryu, Jun Seo, Eun-Young Kang, Jae-Seung Hwang, Sung-Un Kwon
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Publication number: 20110111532Abstract: Methods of forming pattern structures and methods of manufacturing memory devices using the same are provided, the methods of forming pattern structures include forming an etching object layer on a substrate and performing a plasma reactive etching process on the etching object layer using an etching gas including at least ammonia (NH3) gas. The etching object layer includes a magnetic material or a phase change material.Type: ApplicationFiled: November 5, 2010Publication date: May 12, 2011Inventors: Yong-Hwan RYU, Jae-Seung HWANG, Sung-Un KWON, Kyoung-Ha EOM
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Publication number: 20100221921Abstract: Methods of forming patterns in semiconductor devices are provided including forming first patterns spaced apart from one another on an object structure. A first sacrificial layer is formed conformally on the first patterns and the object structure. A second pattern is formed on a sidewall of the first sacrificial layer, the second pattern having a height smaller than that of the first pattern from an upper surface of the object structure. The first patterns are selectively removed to form an opening that exposes the object structure. A third pattern is formed on a sidewall of the opening.Type: ApplicationFiled: March 2, 2010Publication date: September 2, 2010Inventors: Yong-Hyun Kwon, Jun Seo, Jae-Seung Hwang, Ji-Young Lee
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Patent number: 7749902Abstract: Provided is a method of manufacturing a semiconductor device using double patterning. The method includes: forming a first material layer pattern having recesses in a first direction on an object layer and a second material layer pattern formed on the first material layer pattern; selectively etching the second material layer pattern and the first material layer pattern in a direction perpendicular to the first direction to form an etching mask; and etching the object layer to form minute patterns.Type: GrantFiled: June 5, 2007Date of Patent: July 6, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-chul Kim, Sung-il Cho, Jae-seung Hwang, Jun Sen, Yong-hyun Kwon
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Patent number: 7745290Abstract: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.Type: GrantFiled: July 3, 2007Date of Patent: June 29, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun Seo, Jong-Heui Song, Jae-Seung Hwang, Min-Chul Chae, Woo-Jin Cho, Yun-Seung Kang, Young-Mi Lee
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Patent number: 7723191Abstract: A method of manufacturing a semiconductor device having buried gates may include forming a stacked structure of sequentially stacked first mask patterns and second mask patterns with equal widths to expose active regions and isolation regions of a semiconductor substrate. After forming reduced first mask patterns by decreasing the width only of the first mask patterns, trenches may be formed in the active regions and the isolation regions by etching the exposed portions of the semiconductor substrate using the second mask patterns as an etch mask. Then, gate insulating films may be formed on inner walls of the trenches in the active regions, and a conductive material may be buried into the trenches in the active regions and the isolation regions to form gates.Type: GrantFiled: December 13, 2007Date of Patent: May 25, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-young Kang, Jun Seo, Jae-seung Hwang, Sung-il Cho, Yong-hyun Kwon
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Patent number: 7667221Abstract: In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.Type: GrantFiled: February 21, 2007Date of Patent: February 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Heui Song, Yong-Sun Ko, Jae-Seung Hwang, Jun Seo
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Patent number: 7659162Abstract: A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.Type: GrantFiled: October 8, 2008Date of Patent: February 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Soo Lim, Yong-Sun Ko, Sung-Un Kwon, Jae-Seung Hwang
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Patent number: 7534704Abstract: In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.Type: GrantFiled: June 9, 2006Date of Patent: May 19, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Kyu Ha, Jun Seo, Min-Chul Chae, Yong-Sun Ko, Young-Mi Lee, Jae-Seung Hwang
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Patent number: 7531450Abstract: Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.Type: GrantFiled: June 7, 2007Date of Patent: May 12, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Seung Kang, Jun Seo, Min-Chul Chae, Jae-Seung Hwang, Sung-Un Kwon, Woo-Jin Cho
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Publication number: 20090117744Abstract: A method of forming an ion implantation mask includes forming a field area on a semiconductor substrate, forming an amorphous carbon layer on the semiconductor substrate, forming a hard mask layer on the amorphous carbon layer, forming an etching mask pattern on the hard mask layer, and etching the hard mask layer and the amorphous carbon layer to expose the field area through the etching mask pattern, wherein etching the hard mask layer and the amorphous carbon layer forms a hard mask layer pattern and an amorphous carbon layer pattern.Type: ApplicationFiled: October 31, 2008Publication date: May 7, 2009Inventors: Yong-Woo Lee, Young-Mi Lee, Min-Chul Chae, Dae-Joung Kim, Jae-Seung Hwang
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Publication number: 20090090899Abstract: A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.Type: ApplicationFiled: October 8, 2008Publication date: April 9, 2009Inventors: Young-Soo Lim, Yong-Sun Ko, Sung-Un Kwon, Jae-Seung Hwang
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Publication number: 20090020816Abstract: One embodiment generally described herein can be characterized as a semiconductor device. The semiconductor device can include a first transistor on a semiconductor substrate. A first interlayer insulating layer may be disposed over the first transistor and includes a first recess region. A single-crystalline semiconductor pattern may be disposed in the first recess region. A single-crystalline semiconductor plug may connect the semiconductor substrate to the single-crystalline semiconductor pattern. A second transistor may be disposed on the single-crystalline semiconductor pattern.Type: ApplicationFiled: July 17, 2008Publication date: January 22, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo-Jin CHO, Yong-Woo LEE, Jae-Seung HWANG, Sung-Un KWON, Min-Chul CHAE