Abstract: Methods of forming a semiconductor device include forming a structure including an oxide layer, a polysilicon layer and a mask layer on a substrate. The structure is etched to form an opening therein and the substrate beneath the opening to form a trench. An insulating structure is formed in the opening and the trench. The mask is removed and a second polysilicon layer is formed adjacent the second insulating structure. Sidewall portions of the second insulating structure are removed prior to formation of the second polysilicon layer. The thickness of the first polysilicon layer may be chosen based on the desired thickness of the second polysilicon layer. Resulting devices are also disclosed.

Abstract: Disclosed are an etching gas composition for etching silicon oxide and a method of etching silicon oxide using the same. The etching gas composition for etching silicon oxide consists essentially of a carbon fluoride gas, in which the ratio of fluorine atoms relative to carbon atoms is less than 2, and an auxiliary fluorohydrocarbon gas comprising hydrogen, fluorine and carbon atoms. Silicon oxide is etched efficiently and precisely by utilizing a plasma of the etching gas composition. The etching selectivity of an oxide layer formed of silicon oxide with respect to photoresisit is thereby increased. Even when a thin photoresist layer wherein solubility into water changes by a light having DUV wavelength is applied, a contact hole having a high aspect ratio and a good profile can be manufactured using the etching compositions and methods of the present invention.

Abstract: Disclosed are an etching gas composition for etching silicon oxide and a method of etching silicon oxide using the same. The etching gas composition for etching silicon oxide consists essentially of a carbon fluoride gas, in which the ratio of fluorine atoms relative to carbon atoms is less than 2, and an auxiliary fluorohydrocarbon gas comprising hydrogen, fluorine and carbon atoms. Silicon oxide is etched efficiently and precisely by utilizing a plasma of the etching gas composition. The etching selectivity of an oxide layer formed of silicon oxide with respect to photoresisit is thereby increased. Even when a thin photoresist layer wherein solubility into water changes by a light having DUV wavelength is applied, a contact hole having a high aspect ratio and a good profile can be manufactured using the etching compositions and methods of the present invention.

Abstract: A semiconductor device comprising a borderless contract structure and a method of manufacturing the same. An etch-protecting layer is formed on a semiconductor substrate having gate electrodes formed on an active area of the substrate. Spacers are formed on the etch-protecting layer, and removed after performing a source/drain ion-implantation process to secure a region for forming a contact hole between the gate electrodes. After sequentially forming an etch-stopping layer and an insulating interlayer on a resultant structure, the etch-stopping layer and the insulating interlayer are etched to form the first contact hole which exposes a surface of the semiconductor substrate between gate electrodes and a second contact hole for the borderless contact which exposes the surface of the semiconductor substrate adjacent to the field oxide layer and a portion of a surface of the field oxide layer.

Abstract: A method of manufacturing a capacitor having increased capacitance using a single photo-lithographic step to form two holes of different sizes in the insulating layers, wherein a first insulating layer, an etching stop layer, and a second insulating layer are sequentially deposited on a semiconductor substrate, a preliminary hole is formed by etching a predetermined portion of the second insulating layer, the preliminary hole is expanded so as to form a first hole, a second hole is formed extending from the bottom of the first hole and having an etched area narrower than an etched area of the first hole, a first conductive layer pattern is formed on the sidewalls of the first and second holes and at the bottom surface of the second hole without burying the second hole, thereby increasing the storage capacitance of the capacitor while simplifying the manufacturing process.

Abstract: After an etching stop layer and an interlayer dielectric film are formed on a semiconductor substrate including a contact formation portion, a polysilicon film and a anti-reflective layer are successively formed on the interlayer dielectric film. A second mask pattern exposing the polysilicon film is formed after etching the anti-reflective layer exposed through a first mask pattern. A third mask pattern is formed by attaching polymer on a sidewall of the second mask pattern. A contact hole exposing the contact formation portion is formed by etching the polysilicon film and the interlayer dielectric film using the third mask pattern as an etching mask. A conductive material is filled in the contact hole to form the contact. By attaching the polymer to the second mask pattern, a contact hole with a minute size can be formed.

Abstract: In a method for shallow trench isolation and a method for manufacturing a non-volatile memory device using the same, a hard mask layer pattern, a stopper layer pattern and an oxide film pattern are formed by patterning a hard mask layer, a stopper layer and an oxide film. A trench is formed by etching an upper portion of a substrate adjacent to the stopper layer pattern with the hard mask layer pattern. After removing the hard mask layer, a field oxide layer is formed in the trench. After etching the trench with the hard mask, the aspect ratio of the trench region is reduced by removing the hard mask prior to filling the trench, enhancing the gap filling margin of the trench fill process.

Abstract: After an etching stop layer and an interlayer dielectric film are formed on a semiconductor substrate including a contact formation portion, a polysilicon film and a anti-reflective layer are successively formed on the interlayer dielectric film. A second mask pattern exposing the polysilicon film is formed after etching the anti-reflective layer exposed through a first mask pattern. A third mask pattern is formed by attaching polymer on a sidewall of the second mask pattern. A contact hole exposing the contact formation portion is formed by etching the polysilicon film and the interlayer dielectric film using the third mask pattern as an etching mask. A conductive material is filled in the contact hole to form the contact. By attaching the polymer to the second mask pattern, a contact hole with a minute size can be formed.

Abstract: A method for manufacturing a non-volatile memory device including a self-aligned gate structure, and a non-volatile memory device manufactured by the same method, are provided. In the method for manufacturing a non-volatile memory device, a tunnel dielectric layer is formed on a semiconductor substrate. First floating gate patterns are formed on the tunnel dielectric layer. Mold patterns are formed on the first floating gate patterns to selectively expose predetermined portions of the first floating gate patterns. Floating gates are formed by removing the exposed portions of the first floating gate patterns using the mold patterns as a mask. Interlayer dielectric layer patterns are formed for insulating the floating gates from one another by filling gaps between the mold patterns. The mold patterns exposed between the interlayer dielectric layer patterns are formed using the interlayer dielectric layer patterns as an etching mask.

Abstract: In a method for shallow trench isolation and a method for manufacturing a non-volatile memory device using the same, a hard mask layer pattern, a stopper layer pattern and an oxide film pattern are formed by patterning a hard mask layer, a stopper layer and an oxide film. A trench is formed by etching an upper portion of a substrate adjacent to the stopper layer pattern with the hard mask layer pattern. After removing the hard mask layer, a field oxide layer is formed in the trench. After etching the trench with the hard mask, the aspect ratio of the trench region is reduced by removing the hard mask prior to filling the trench, enhancing the gap filling margin of the trench fill process.

Abstract: A method of forming electric wiring using a dual damascene process wherein prevention of damage to a lower conductive pattern and low contact resistance may be achieved. A first insulation layer having a first trench filled with a conductive material is formed on a semiconductor substrate. A first etch stop layer, a second insulation layer and a third insulation layer are sequentially formed thereon. A capping layer is formed on the third insulation layer. A via hole is formed by selectively etching the capping layer, third insulation layer and second insulation layer. Then the capping layer is partially etched and a polymer layer is formed on the exposed first etch stop layer. A second trench is formed and the electric wiring is formed by filling a conductive material in a resulting structure. The polymer layer prevents damage to the conductive pattern by protecting the first etch stop layer.

Abstract: A floating gate electrode configuration and process reduces a space critical dimension between adjacent floating gate electrodes while reducing the consumption of a device isolation layer during etching of a dielectric layer overlying the floating gate electrode. The end portions of the floating gate electrode, which is formed separated on a device isolation region, have a step or rounded pattern. In order to realize such a pattern, after a first partial etch of a floating gate electrode material, polymer spacers or silicon nitride spacers are formed along the etched sidewalls. Then, using those spacers as an etching mask, a second etch is performed on the floating gate electrode material to separate the same. Furthermore, after forming polysilicon on the partially etched floating gate electrode material, blanket etching is performed on the polysilicon to form a floating gate electrode having a round pattern of end portions.

Abstract: A method of forming a mask comprises forming a mask layer including nitrogen, forming a photoresist pattern on the mask layer and etching the mask layer using a mixes gas including a first gas adapted for etching the mask layer and a second gas for increasing selectivity of the photoresist pattern, thereby forming a hard mask. In this manner, selectivity of the photoresist is improved while a high etching ratio of the nitride layer is maintained when forming a hard mask.

Abstract: A method for manufacturing a non-volatile memory device including a self-aligned gate structure, and a non-volatile memory device manufactured by the same method, are provided. In the method for manufacturing a non-volatile memory device, a tunnel dielectric layer is formed on a semiconductor substrate. First floating gate patterns are formed on the tunnel dielectric layer. Mold patterns are formed on the first floating gate patterns to selectively expose predetermined portions of the first floating gate patterns. Floating gates are formed by removing the exposed portions of the first floating gate patterns using the mold patterns as a mask. Interlayer dielectric layer patterns are formed for insulating the floating gates from one another by filling gaps between the mold patterns. The mold patterns exposed between the interlayer dielectric layer patterns are formed using the interlayer dielectric layer patterns as an etching mask.

Abstract: A floating gate electrode configuration and process reduces a space critical dimension between adjacent floating gate electrodes while reducing the consumption of a device isolation layer during etching of a dielectric layer overlying the floating gate electrode. The end portions of the floating gate electrode, which is formed separated on a device isolation region, have a step or rounded pattern. In order to realize such a pattern, after a first partial etch of a floating gate electrode material, polymer spacers or silicon nitride spacers are formed along the etched sidewalls. Then, using those spacers as an etching mask, a second etch is performed on the floating gate electrode material to separate the same. Furthermore, after forming polysilicon on the partially etched floating gate electrode material, blanket etching is performed on the polysilicon to form a floating gate electrode having a round pattern of end portions.

Abstract: Disclosed is a method of forming electric wiring using a dual damascene process wherein prevention of damage to a lower conductive pattern and low contact resistance may be achieved. A first insulation layer having a first trench filled with a conductive material is formed on a semiconductor substrate. A first etch stop layer, a second insulation layer and a third insulation layer are sequentially formed thereon. A capping layer is formed on the third insulation layer. A via hole is formed by selectively etching the capping layer, third insulation layer and second insulation layer. Then the capping layer is partially etched and a polymer layer is formed on the exposed first etch stop layer. A second trench is formed and the electric wiring is formed by filling a conductive material in a resulting structure. The polymer layer prevents damage to the conductive pattern by protecting the first etch stop layer.

Abstract: A semiconductor device comprising a borderless contract structure and a method of manufacturing the same. An etch-protecting layer is formed on a semiconductor substrate having gate electrodes formed on an active area of the substrate. Spacers are formed on the etch-protecting layer, and removed after performing a source/drain ion-implantation process to secure a region for forming a contact hole between the gate electrodes. After sequentially forming an etch-stopping layer and an insulating interlayer on a resultant structure, the etch-stopping layer and the insulating interlayer are etched to form the first contact hole which exposes a surface of the semiconductor substrate between gate electrodes and a second contact hole for the borderless contact which exposes the surface of the semiconductor substrate adjacent to the field oxide layer and a portion of a surface of the field oxide layer.

Abstract: A floating gate electrode configuration and process reduces a space critical dimension between adjacent floating gate electrodes while reducing the consumption of a device isolation layer during etching of a dielectric layer overlying the floating gate electrode. The end portions of the floating gate electrode, which is formed separated on a device isolation region, have a step or rounded pattern. In order to realize such a pattern, after a first partial etch of a floating gate electrode material, polymer spacers or silicon nitride spacers are formed along the etched sidewalls. Then, using those spacers as an etching mask, a second etch is performed on the floating gate electrode material to separate the same. Furthermore, after forming polysilicon on the partially etched floating gate electrode material, blanket etching is performed on the polysilicon to form a floating gate electrode having a round pattern of end portions.

Abstract: A method of manufacturing a capacitor having increased capacitance using a single photo-lithographic step to form two holes of different sizes in the insulating layers, wherein a first insulating layer, an etching stop layer, and a second insulating layer are sequentially deposited on a semiconductor substrate, a preliminary hole is formed by etching a predetermined portion of the second insulating layer, the preliminary hole is expanded so as to form a first hole, a second hole is formed extending from the bottom of the first hole and having an etched area narrower than an etched area of the first hole, a first conductive layer pattern is formed on the sidewalls of the first and second holes and at the bottom surface of the second hole without burying the second hole, thereby increasing the storage capacitance of the capacitor while simplifying the manufacturing process.

Abstract: Disclosed are an etching gas composition for etching silicon oxide and a method of etching silicon oxide using the same. The etching gas composition for etching silicon oxide consists essentially of a carbon fluoride gas, in which the ratio of fluorine atoms relative to carbon atoms is less than 2, and an auxiliary fluorohydrocarbon gas comprising hydrogen, fluorine and carbon atoms. Silicon oxide is etched efficiently and precisely by utilizing a plasma of the etching gas composition. The etching selectivity of an oxide layer formed of silicon oxide with respect to photoresisit is thereby increased. Even when a thin photoresist layer wherein solubility into water changes by a light having DUV wavelength is applied, a contact hole having a high aspect ratio and a good profile can be manufactured using the etching compositions and methods of the present invention.