Abstract: A floating gate electrode configuration and process reduces a space critical dimension between adjacent floating gate electrodes while reducing the consumption of a device isolation layer during etching of a dielectric layer overlying the floating gate electrode. The end portions of the floating gate electrode, which is formed separated on a device isolation region, have a step or rounded pattern. In order to realize such a pattern, after a first partial etch of a floating gate electrode material, polymer spacers or silicon nitride spacers are formed along the etched sidewalls. Then, using those spacers as an etching mask, a second etch is performed on the floating gate electrode material to separate the same. Furthermore, after forming polysilicon on the partially etched floating gate electrode material, blanket etching is performed on the polysilicon to form a floating gate electrode having a round pattern of end portions.