Abstract: Disclosed is a structure and a method of forming the structure. The structure includes first and second semiconductor substrates with adjacent surfaces (e.g., bonded surfaces), a first spiral-shape metallic feature in the first semiconductor substrate, and a second spiral-shaped metallic feature in the second semiconductor substrate. The second spiral-shaped metallic feature is aligned above and electrically connected to the first spiral-shaped metallic feature. In some embodiments, the second spiral-shaped metallic feature is stacked on and immediately adjacent to the first spiral-shaped metallic feature at the bonded surfaces, thereby forming a relatively large inductor with high Qdc in a relatively small area. In other embodiments, the first and second spiral-shaped metallic features are discrete inductors located on opposite sides of the semiconductor substrates from the bonded surfaces but electrically connected in parallel (e.g.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

Abstract: A disclosed structure includes a fin-based bipolar junction transistor (BJT) with reduced base resistance. The BJT includes one or more semiconductor fins. Each semiconductor fin has opposing sidewalls, a first width, and a base recess, which extends across the first width through the opposing sidewalls. The BJT includes a base region positioned laterally between collector and emitter regions. The base region includes a base semiconductor layer (e.g., an intrinsic base layer), which fills the base recess and which has a second width greater than the first width such that the base semiconductor layer extends laterally beyond the opposing sidewalls. In a BJT with multiple semiconductor fins, the base recess on each semiconductor fin is filled with a discrete base semiconductor layer. The base region further includes an additional base semiconductor layer (e.g., an extrinsic base layer) covering the base semiconductor layer(s). Also disclosed is a method of forming the structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region within a semiconductor substrate material; a shallow trench isolation structure extending into the semiconductor substrate material and bounding the extrinsic base region; an emitter region adjacent to the shallow trench isolation structure and on a side of the extrinsic base region; and a collector region adjacent to the shallow trench isolation structure and on an opposing side of the extrinsic base region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

Abstract: A disclosed structure includes a FET with a gate structure (e.g., a RMG structure) having a scaled effective gate length proximal to a channel region and a large conductor surface distal to the channel region. The gate structure includes a first portion within a lower region of a gate opening proximal to the channel region and a second portion within a wider upper region. In this case, the gate structure can include a conformal gate dielectric layer that lines the gate opening and a gate conductor layer thereon. Alternatively, the gate structure includes a first portion including a short gate dielectric layer proximal to the channel region and a second portion (including a conformal gate dielectric layer and gate conductor layer) on the lower portion in a gate opening. Optionally, the structure also includes an additional FET without the scaled effective gate length. Also disclosed are associated methods.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an emitter in a semiconductor substrate; a collector in the semiconductor substrate; a base contact region in the semiconductor substrate and adjacent to the collector and the emitter; and a shallow trench isolation structure overlapping the base contact region and separating the base contact region from the emitter and the collector.

Abstract: A transistor structure includes a semiconductor substrate with a source region and a drain region therein that are asymmetric. A gate dielectric structure includes a first gate oxide region over a portion of the source region, a second gate oxide region over a portion of the drain region, and a high dielectric constant (high-K) dielectric layer contacting the semiconductor substrate and separating the first gate oxide region from the second gate oxide region. A gate body is over the gate dielectric structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a dielectric layer having a cavity, a first semiconductor layer on the dielectric layer, a collector including a portion on the first semiconductor layer, an emitter including a portion on the first semiconductor layer, and a second semiconductor layer that includes a first section in the cavity and a second section. The second section of the second semiconductor layer is laterally positioned between the portion of the collector and the portion of the emitter.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes a lateral bipolar junction transistor including an extrinsic base region and a bilayer dielectric spacer on sidewalls of the extrinsic base region, and a p-n junction positioned under the bilayer dielectric spacer between the extrinsic base region and at least an emitter region.

Abstract: Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region composed of semiconductor material; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and an extrinsic base contact wrapping around the semiconductor material of the extrinsic base region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to annular bipolar transistors and methods of manufacture. The structure includes: a substate material; a collector region parallel to and above the substrate material; an intrinsic base region surrounding the collector region; an emitter region above the intrinsic base region; and an extrinsic base region contacting the intrinsic base region.

Abstract: The disclosure provides a lateral bipolar transistor structure with a base layer over a semiconductor buffer, and related methods. A lateral bipolar transistor structure may include an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A semiconductor buffer is adjacent the insulator. A base layer is on the semiconductor buffer and adjacent the E/C layer, the base layer including a lower surface below the E/C layer and an upper surface above the E/C layer. The base layer has a second doping type opposite the first doping type.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a laterally diffused metal-oxide semiconductor with one or more gate contacts and methods of manufacture. The structure includes: sidewall spacers over a semiconductor substrate; and a gate structure within a space defined by the sidewall spacers. The gate structure includes: a plurality of gate materials over the semiconductor substrate and between the sidewall spacers; and a gate electrode over the plurality of gate materials and contacting the sidewall spacers.

Abstract: A structure has a substrate, a drift region within the substrate, a semiconductor-on-insulator structure on the substrate adjacent to the drift region, a gate insulator layer having a first portion on the substrate and a second portion extending over the semiconductor-on-insulator structure, a gate conductor on the first portion, and a field plate on the gate conductor and the second portion.

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer having a top surface and a side surface, a second terminal having a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The structure further includes a contact positioned to overlap with the top surface and the side surface of the first raised semiconductor layer.

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a collector having a raised portion, an emitter having a raised portion, and a base laterally arranged between the raised portion of the emitter and the raised portion of the collector. The base includes an intrinsic base layer and an extrinsic base layer stacked with the intrinsic base layer. The structure further includes a stress liner positioned to overlap with the raised portion of the collector, the raised portion of the emitter, and the extrinsic base layer.