Abstract: Disclosed is a structure and a method of forming the structure. The structure includes first and second semiconductor substrates with adjacent surfaces (e.g., bonded surfaces), a first spiral-shape metallic feature in the first semiconductor substrate, and a second spiral-shaped metallic feature in the second semiconductor substrate. The second spiral-shaped metallic feature is aligned above and electrically connected to the first spiral-shaped metallic feature. In some embodiments, the second spiral-shaped metallic feature is stacked on and immediately adjacent to the first spiral-shaped metallic feature at the bonded surfaces, thereby forming a relatively large inductor with high Qdc in a relatively small area. In other embodiments, the first and second spiral-shaped metallic features are discrete inductors located on opposite sides of the semiconductor substrates from the bonded surfaces but electrically connected in parallel (e.g.

Abstract: A disclosed structure includes a FET with a gate structure (e.g., a RMG structure) having a scaled effective gate length proximal to a channel region and a large conductor surface distal to the channel region. The gate structure includes a first portion within a lower region of a gate opening proximal to the channel region and a second portion within a wider upper region. In this case, the gate structure can include a conformal gate dielectric layer that lines the gate opening and a gate conductor layer thereon. Alternatively, the gate structure includes a first portion including a short gate dielectric layer proximal to the channel region and a second portion (including a conformal gate dielectric layer and gate conductor layer) on the lower portion in a gate opening. Optionally, the structure also includes an additional FET without the scaled effective gate length. Also disclosed are associated methods.

Abstract: FET designs, and in particular NMOSFET designs based on SOI fabrication technology, that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments include FETs in which the threshold voltage VTE of the edge FETs is increased to a level that is at least equal to the threshold voltage VTC of the central conduction channel FET using a novel dual work function configuration of a high dielectric constant (high-?) replacement metal gate (RMG) structure. One embodiment encompasses a FET including an RMG structure overlying a doped silicon region, the RMG structure including: an interface insulator formed over the doped silicon region; a high-K material formed over the interface insulator; an N-type work function material overlaying and in contact with a central portion of the high-? material; and a P-type work function material overlaying and in contact with at least one edge portion of the high-? material.

Abstract: Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer “T”-shaped gate (as viewed in cross-section). The novel “T-gate” significantly decreases the gate resistance RG of a MOSFET device and thus increases the figure-of-merit fMAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths Lg scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance CGS and gate-to-drain capacitance CGD, with concomitant improved performance at high radio frequencies (RF).

Abstract: MOSFET-based IC architectures that mitigate or eliminate the relatively high resistance of extended drift regions in EDMOS and LDMOS devices, resulting in MOSFETs that are reliable, capable of handling relatively high drain voltages, and provide high currents at relatively low drain voltages. Embodiments encompass EDMOS or LDMOS devices that include a secondary transistor comprising a differently-doped well located adjacent at least one drift region and between the drain and the body of the device, with a variably-biased secondary gate structure aligned over the differently doped well. Biasing the secondary gate structure to an OFF state causes the differently-doped well to exhibit high resistance, resulting in a high breakdown voltage for the device. Biasing the secondary gate structure to an ON state causes the differently-doped well to exhibit low resistance, resulting in a reduced drain resistance path that improves the linearity and the error-vector magnitude characteristics of the device.

Abstract: Novel NEDMOS and/or LDMOS FET integrated circuit structures that reduce or eliminate the floating body effect by reducing the built-in voltage Vbi of the device. Reduction of Vbi includes adding a source-side structure that includes a “Vbi Reduction Material” (VRM) layer. VRM has a bandgap less than the bandgap of Si and, for an N-type device, a valence band that is higher than the valence band of the body material. The low Vbi of the VRM layer on the source-side of a MOSFET device that would otherwise exhibit a floating body effect allows significantly freer movement of holes from the body of the device towards the source region, thus increasing body hole collection efficiency, and significantly reduces the floating body effect.

Abstract: A P-type Extended Drain MOS (PEDMOS) FETs capable of high speed operation and the capability to withstand relatively high drain voltages. The PEDMOS device includes an active layer (preferably <110> orientated Si) having a P+ SiGe source region, a first P? Si drift region, a second P? SiGe drift region, and a P+ SiGe drain region. The SiGe regions exert compression on the N-type Si channel, improving hole mobility within the PEDMOS device and resulting in low leakage currents at active layer edges, low channel resistance, and good HCI and GIDL characteristics. Forming the SiGe regions may include etching voids in the Si active layer and depositing SiGe within the voids; implanting Ge into defined regions of the Si active layer; or etching partial voids in the Si active layer, depositing SiGe within the partial voids in contact with Si, and diffusing the Ge into the Si.

Abstract: A number of MOSFET architectures provide high-voltage capability (both drain-source breakdown voltage BVDSS and ON-state breakdown voltage BVON), low current leakage, and extended linearity. Embodiments of the invention overcome the limitations of conventional NEDMOS and LDMOS device designs by providing a low-resistance path for hole collection and by purposefully exhibiting multiple voltage thresholds VTH in different segments of the device. Embodiments includes NEDMOS and LDMOS device designs having multiple body contact regions for improved hole collection, sub-gate doped stripes or segments for even better hole collection and linearity, and sub-gate doped edge regions for increased local VTH and thus decreased current leakage. P? hole-collection stripes and P+ body contact regions may be formed of a semiconductor material that includes germanium. The inventive MOSFETs may be arranged as multi-MOSFET array elements, and multiple array elements may be arranged in a larger array.

Abstract: An integrated circuit includes a substrate, a metal layer positioned above the substrate, an oxide layer disposed between the substrate and the metal layer, and a transistor disposed on the substrate between the substrate and the oxide layer. The transistor includes a source, a gate, and a drain. A dummy contact is positioned within the oxide layer above and in thermal contact with the gate of transistor. The dummy contact is electrically isolated and configured to convey heat generated by the transistor during operation of the integrated circuit to the metal layer.

Abstract: In accordance with various embodiments, a method for fabricating a device is provided. The method includes providing a semiconductor layer-stack having one or more layers and a high resistivity substrate layer; implanting a first dopant to form a first region; etching one or more vias through the one or more layers and into a top portion of the high resistivity substrate layer; implanting a second dopant to form one or more second regions; and implanting the first dopant to form one or more third regions. The method also includes depositing a metal in the vias to form one or more metal contacts, thereby forming a diode or a bipolar junction transistor. Either the second or third regions can include a floating region to improve the transistor performance. The transistor can be a PNP or a NPN bipolar junction transistor, depending on the dopants.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a laterally diffused metal-oxide semiconductor with one or more gate contacts and methods of manufacture. The structure includes: sidewall spacers over a semiconductor substrate; and a gate structure within a space defined by the sidewall spacers. The gate structure includes: a plurality of gate materials over the semiconductor substrate and between the sidewall spacers; and a gate electrode over the plurality of gate materials and contacting the sidewall spacers.

Abstract: An IC structure that includes a trench isolation (TI) in a substrate having three portions of different dielectric materials. The portions may also have different widths. The TI may include a lower portion including a first dielectric material and having a first width, a middle portion including the first dielectric material and an outer second dielectric material, and an upper portion including a third dielectric material and having a second width greater than the first width. The first, second and third dielectric materials are different.

Abstract: MOSFET-based IC architectures, including SOI NEDMOS ICs and bulk semiconductor LDMOS ICs, that mitigate or eliminate the problems of edge transistors. One IC embodiment includes end-cap body contact regions angle-implanted to have a first characteristic (e.g., P+), a drift region, and a gate structure partially overlying the end-cap body contact regions and the drift region and including a conductive layer having a third characteristic (e.g., N+) and a first side angle-implanted to have the first characteristic. Steps for fabricating such an IC include implanting a dopant at an angle in the range of about 5° to about 60° within the end-cap body contact regions and within the first side of the conductive layer in a region of the gate structure overlying the end-cap body contact regions, wherein the angle-implanted dopant results in the first characteristic for the end-cap body contact regions and the first side of the conductive layer.

Abstract: Structures and methods for better optimizing the performance of all the circuitry of an SOI IC. Embodiments include SOI IC having dual-thickness active areas, such that digital and non-RF analog circuitry may be fabricated on a relatively thin active layer while RF circuitry may be fabricated on a relatively thick active layer. Fabrication of RF circuitry on the relatively thick active layer allows for improvements to the RON*COFF figure of merit for the FET devices, and for optimizations not feasible for RF circuitry fabricated on a relatively thin active layer. Structures and methods for two-level shallow-trench isolation (STI) structures and electrical contacts are disclosed. Some embodiments may include a substrate contact extending from the substantially planar upper surface of a dielectric layer overlaying the thin and thick active areas to at least the BOX layer.

Abstract: Integrated circuit structures that significantly reduce the resistance associated with the body contact region and substrate region contact of a field-effect transistor (FET) compared to conventional designs. Embodiments include a FET having a body contact region, and optionally a substrate region contact, that includes germanium (Ge) alone or as an alloy with silicon (SiGe) and/or as a layered combination with silicon (e.g., a layer of Ge on a layer of Si). A first method includes fabricating a body contact region of a field-effect transistor by fabricating the field-effect transistor with an Si body contact region, and diffusing or implanting Ge within the Si. A second method includes fabricating a body contact region of a field-effect transistor by fabricating the field-effect transistor with an Si body contact region, etching away at least part of the Si body contact region to form a well, and depositing Ge within the well.

Abstract: Structures and methods for better optimizing the performance of all the circuitry of an SOI IC. Embodiments include SOI IC having dual-thickness active areas, such that digital and non-RF analog circuitry may be fabricated on a relatively thin active layer while RF circuitry may be fabricated on a relatively thick active layer. Fabrication of RF circuitry on the relatively thick active layer allows for improvements to the RON*COFF figure of merit for the FET devices, and for optimizations not feasible for RF circuitry fabricated on a relatively thin active layer. Two methods of forming shallow-trench isolation (STI) structures in both active layers are described. A first method forms STIs in the thin active layer first, then in the thick active layer. A second method forms STIs in the thin active layer first and partial STIs in the thick active layer, then completes the partial STIs in the thick active layer.

Abstract: High-voltage transistors that may be fabricated in a standard low-voltage process. Embodiments include integrated circuits that combine, in a unitary structure, an LDMOS FET device that includes one or more dummy polysilicon structures (DPS's) overlying a drift region and comparable in configuration to the FET gate, and interstitial implant resistance pockets (IRP) formed within the drift region between the gate and an adjacent DPS and between each pair of adjacent DPS's. The IRPs may be augmented with floating contacts to remove heat from the drift region and provide additional shielding of the drain contact from the nearest edge of the gate. The IRPs may be biased to modulate the conductivity of the drift region. The DPS's may be biased to modulate the conductivity of the drift region, and in such a way as to protect each DPS from excessive and potentially destructive voltages.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an emitter in a semiconductor substrate; a collector in the semiconductor substrate; a base contact region in the semiconductor substrate and adjacent to the collector and the emitter; and a shallow trench isolation structure overlapping the base contact region and separating the base contact region from the emitter and the collector.