Patents by Inventor Jagar Singh

Jagar Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240047555
    Abstract: A disclosed structure includes a FET with a gate structure (e.g., a RMG structure) having a scaled effective gate length proximal to a channel region and a large conductor surface distal to the channel region. The gate structure includes a first portion within a lower region of a gate opening proximal to the channel region and a second portion within a wider upper region. In this case, the gate structure can include a conformal gate dielectric layer that lines the gate opening and a gate conductor layer thereon. Alternatively, the gate structure includes a first portion including a short gate dielectric layer proximal to the channel region and a second portion (including a conformal gate dielectric layer and gate conductor layer) on the lower portion in a gate opening. Optionally, the structure also includes an additional FET without the scaled effective gate length. Also disclosed are associated methods.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 8, 2024
    Inventors: Anton V. Tokranov, Saloni Chaurasia, Hong Yu, Jagar Singh
  • Publication number: 20240030320
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an emitter in a semiconductor substrate; a collector in the semiconductor substrate; a base contact region in the semiconductor substrate and adjacent to the collector and the emitter; and a shallow trench isolation structure overlapping the base contact region and separating the base contact region from the emitter and the collector.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Inventor: Jagar SINGH
  • Publication number: 20240030343
    Abstract: A transistor structure includes a semiconductor substrate with a source region and a drain region therein that are asymmetric. A gate dielectric structure includes a first gate oxide region over a portion of the source region, a second gate oxide region over a portion of the drain region, and a high dielectric constant (high-K) dielectric layer contacting the semiconductor substrate and separating the first gate oxide region from the second gate oxide region. A gate body is over the gate dielectric structure.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Inventors: Saloni Chaurasia, Man Gu, Jagar Singh
  • Publication number: 20240021713
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Inventors: Haiting Wang, Alexander Derrickson, Jagar Singh, Vibhor Jain, Andreas Knorr, Alexander Martin, Judson R. Holt, Zhenyu Hu
  • Patent number: 11848374
    Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a dielectric layer having a cavity, a first semiconductor layer on the dielectric layer, a collector including a portion on the first semiconductor layer, an emitter including a portion on the first semiconductor layer, and a second semiconductor layer that includes a first section in the cavity and a second section. The second section of the second semiconductor layer is laterally positioned between the portion of the collector and the portion of the emitter.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: December 19, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Shesh Mani Pandey, Jagar Singh, Judson Holt
  • Patent number: 11843034
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes a lateral bipolar junction transistor including an extrinsic base region and a bilayer dielectric spacer on sidewalls of the extrinsic base region, and a p-n junction positioned under the bilayer dielectric spacer between the extrinsic base region and at least an emitter region.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: December 12, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Man Gu, Haiting Wang, Jagar Singh
  • Patent number: 11837460
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region composed of semiconductor material; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and an extrinsic base contact wrapping around the semiconductor material of the extrinsic base region.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: December 5, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Jagar Singh, Alexander M. Derrickson, Alexander Martin
  • Patent number: 11837653
    Abstract: Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: December 5, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Jagar Singh, Alexander M. Derrickson, Alvin J. Joseph, Andreas Knorr, Judson R. Holt
  • Patent number: 11810969
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: November 7, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Haiting Wang, Alexander Derrickson, Jagar Singh, Vibhor Jain, Andreas Knorr, Alexander Martin, Judson R. Holt, Zhenyu Hu
  • Patent number: 11804542
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to annular bipolar transistors and methods of manufacture. The structure includes: a substate material; a collector region parallel to and above the substrate material; an intrinsic base region surrounding the collector region; an emitter region above the intrinsic base region; and an extrinsic base region contacting the intrinsic base region.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: October 31, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Alexander M. Derrickson, Arkadiusz Malinowski, Jagar Singh, Mankyu Yang, Judson R. Holt
  • Patent number: 11784224
    Abstract: The disclosure provides a lateral bipolar transistor structure with a base layer over a semiconductor buffer, and related methods. A lateral bipolar transistor structure may include an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A semiconductor buffer is adjacent the insulator. A base layer is on the semiconductor buffer and adjacent the E/C layer, the base layer including a lower surface below the E/C layer and an upper surface above the E/C layer. The base layer has a second doping type opposite the first doping type.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: October 10, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Hong Yu, Jagar Singh, Zhenyu Hu, John J. Pekarik
  • Publication number: 20230317815
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a laterally diffused metal-oxide semiconductor with one or more gate contacts and methods of manufacture. The structure includes: sidewall spacers over a semiconductor substrate; and a gate structure within a space defined by the sidewall spacers. The gate structure includes: a plurality of gate materials over the semiconductor substrate and between the sidewall spacers; and a gate electrode over the plurality of gate materials and contacting the sidewall spacers.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventor: Jagar SINGH
  • Publication number: 20230307539
    Abstract: A structure has a substrate, a drift region within the substrate, a semiconductor-on-insulator structure on the substrate adjacent to the drift region, a gate insulator layer having a first portion on the substrate and a second portion extending over the semiconductor-on-insulator structure, a gate conductor on the first portion, and a field plate on the gate conductor and the second portion.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Applicant: GlobalFoundries U.S. Inc.
    Inventor: Jagar Singh
  • Patent number: 11769806
    Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer having a top surface and a side surface, a second terminal having a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The structure further includes a contact positioned to overlap with the top surface and the side surface of the first raised semiconductor layer.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: September 26, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Hong Yu, Jagar Singh
  • Patent number: 11721722
    Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a collector having a raised portion, an emitter having a raised portion, and a base laterally arranged between the raised portion of the emitter and the raised portion of the collector. The base includes an intrinsic base layer and an extrinsic base layer stacked with the intrinsic base layer. The structure further includes a stress liner positioned to overlap with the raised portion of the collector, the raised portion of the emitter, and the extrinsic base layer.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: August 8, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Man Gu, Jagar Singh, Haiting Wang, Jeffrey Johnson
  • Publication number: 20230238428
    Abstract: An IC structure that includes a trench isolation (TI) in a substrate having three portions of different dielectric materials. The portions may also have different widths. The TI may include a lower portion including a first dielectric material and having a first width, a middle portion including the first dielectric material and an outer second dielectric material, and an upper portion including a third dielectric material and having a second width greater than the first width. The first, second and third dielectric materials are different.
    Type: Application
    Filed: January 24, 2022
    Publication date: July 27, 2023
    Inventors: Rong-Ting Liou, Man Gu, Jeffrey B. Johnson, Wang Zheng, Jagar Singh, Haiting Wang
  • Patent number: 11710771
    Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes an emitter having a raised portion, a collector having a raised portion, and a base having a base layer and an extrinsic base layer stacked with the base layer. The base layer and the extrinsic base layer are positioned in a lateral direction between the raised portion of the emitter and the raised portion of the collector, the base layer has a first width in the lateral direction, the extrinsic base layer has a second width in the lateral direction, and the second width is greater than the first width.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: July 25, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Alexander Derrickson, Judson R. Holt, Haiting Wang, Jagar Singh, Vibhor Jain
  • Patent number: 11652142
    Abstract: A structure for a lateral bipolar junction transistor is provided. The structure comprising an emitter including a first concentration of a first dopant. A collector including a second concentration of the first dopant, the first concentration of the first dopant may be different from the second concentration of the first dopant. An intrinsic base may be laterally arranged between the emitter and the collector, and an extrinsic base region may be above the intrinsic base. An emitter extension may be arranged adjacent to the emitter, whereby the emitter extension laterally extends under a portion of the extrinsic base region. A halo region may be arranged adjacent to the emitter extension, whereby the halo region laterally extends under another portion of the extrinsic base region.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: May 16, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Mankyu Yang, Richard Taylor, III, Alexander Derrickson, Alexander Martin, Jagar Singh, Judson Robert Holt, Haiting Wang
  • Publication number: 20230092435
    Abstract: A structure for a lateral bipolar junction transistor is provided. The structure comprising an emitter including a first concentration of a first dopant. A collector including a second concentration of the first dopant, the first concentration of the first dopant may be different from the second concentration of the first dopant. An intrinsic base may be laterally arranged between the emitter and the collector, and an extrinsic base region may be above the intrinsic base. An emitter extension may be arranged adjacent to the emitter, whereby the emitter extension laterally extends under a portion of the extrinsic base region. A halo region may be arranged adjacent to the emitter extension, whereby the halo region laterally extends under another portion of the extrinsic base region.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: MANKYU YANG, RICHARD TAYLOR, III, ALEXANDER DERRICKSON, ALEXANDER MARTIN, JAGAR SINGH, JUDSON ROBERT HOLT, HAITING WANG
  • Publication number: 20230084007
    Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a dielectric layer having a cavity, a first semiconductor layer on the dielectric layer, a collector including a portion on the first semiconductor layer, an emitter including a portion on the first semiconductor layer, and a second semiconductor layer that includes a first section in the cavity and a second section. The second section of the second semiconductor layer is laterally positioned between the portion of the collector and the portion of the emitter.
    Type: Application
    Filed: January 13, 2022
    Publication date: March 16, 2023
    Inventors: Shesh Mani Pandey, Jagar Singh, Judson Holt