Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.

Abstract: One illustrative method of forming heterojunction bipolar devices includes, among other things, forming a first gate structure above an active semiconductor layer, forming a second gate structure adjacent a first side of the first gate structure, forming a third gate structure adjacent a second side of the first gate structure, forming an emitter of a bipolar transistor in the active semiconductor layer between the first gate structure and the second gate structure, forming a collector of the bipolar transistor in the active semiconductor layer between the first gate structure and the third gate structure, and forming a first base contact contacting the active region adjacent an end of the first gate structure, wherein a portion of the active semiconductor layer positioned under the first gate structure defines a base of the bipolar transistor.

Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.

Abstract: One device disclosed herein includes, among other things, first and second conductive features embedded in a first dielectric layer, a cap layer positioned above the first dielectric layer, a ballistic transport material contacting the first conductive member and positioned above a portion of the first dielectric layer, and first and second contacts contacting the first and second conductive features.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.

Abstract: Structures for switches and methods for forming structures that include a switch. A first well and a section well are arranged in a substrate. Trench isolation regions are arranged in the substrate to define multiple active device regions. Each of the active device regions includes a section of the first well that is surrounded by the trench isolation regions. The second well has an opposite conductivity type from the first well. The active device regions and the trench isolation regions are arranged between the top surface of the substrate and the second well, and the second well is contiguous with the trench isolation regions.

Abstract: One device disclosed herein includes, among other things, first and second conductive features embedded in a first dielectric layer, a cap layer positioned above the first dielectric layer, a ballistic transport material contacting the first conductive member and positioned above a portion of the first dielectric layer, and first and second contacts contacting the first and second conductive features.

Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a laterally-diffused metal-oxide-semiconductor device. A fin projects from a substrate, a channel region and a drain extension are arranged in a first section of the fin and the substrate beneath the first section of the fin, a source region is arranged in the first section of the fin, a drain region is arranged in a second section of the fin and the substrate beneath the second section of the fin, and a gate structure is arranged over the channel region. The drain region and the source region have an opposite conductivity type from the channel region. A trench isolation region is arranged in the fin between the first section of the fin and the second section of the fin. A dummy gate is arranged over a portion of the second section of the fin.

Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a laterally-diffused metal-oxide-semiconductor device. A fin projects from a substrate, a channel region and a drain extension are arranged in a first section of the fin and the substrate beneath the first section of the fin, a source region is arranged in the first section of the fin, a drain region is arranged in a second section of the fin and the substrate beneath the second section of the fin, and a gate structure is arranged over the channel region. The drain region and the source region have an opposite conductivity type from the channel region. A trench isolation region is arranged in the fin between the first section of the fin and the second section of the fin. A dummy gate is arranged over a portion of the second section of the fin.

Abstract: One illustrative device disclosed herein includes a transistor formed above a semiconductor-on-insulator (SOI) substrate, wherein the transistor comprises a gate structure, a sidewall spacer and source/drain regions, openings formed in the active layer in the source/drain regions adjacent the sidewall spacer, recesses formed in a buried insulation layer of the SOI substrate in the source/drain regions of the transistor, wherein the recesses extend laterally under a portion of the active layer, and an epi semiconductor material positioned in at least the recesses in the buried insulation layer.

Abstract: Methods, apparatus, and systems for forming a semiconductor substrate comprising a well region containing a first impurity; forming a gate on the semiconductor substrate above the well region; implanting a second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first concentration; removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions; and growing epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises the second impurity having a second concentration greater than the first concentration.

Abstract: Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.

Abstract: Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.

Abstract: Methods, apparatus, and systems for forming a semiconductor substrate comprising a well region containing a first impurity; forming a gate on the semiconductor substrate above the well region; implanting a second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first concentration; removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions; and growing epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises the second impurity having a second concentration greater than the first concentration.

Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.

Abstract: Structures for switches and methods for forming structures that include a switch. A first well and a section well are arranged in a substrate. Trench isolation regions are arranged in the substrate to define multiple active device regions. Each of the active device regions includes a section of the first well that is surrounded by the trench isolation regions. The second well has an opposite conductivity type from the first well. The active device regions and the trench isolation regions are arranged between the top surface of the substrate and the second well, and the second well is contiguous with the trench isolation regions.

Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.

Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.

Abstract: An LDFET may be formed on the basis of manufacturing platforms designed for forming sophisticated small signal transistor elements. To this end, sidewall areas of trench isolation regions laterally positioned within the drift region may be used as current paths, thereby achieving increased design flexibility, since efficient current paths may still be established, even if the trench isolation regions have to extend into the substrate material due to design criteria determined by the sophisticated small signal transistor elements. In some illustrative embodiments, isolation of P-LDFETs with respect to the P-substrate may be accomplished without requiring a deep well implantation.

Abstract: Methods of forming a hybrid electrically programmable fuse (e-fuse) structure and the hybrid e-fuse structure are disclosed. In various embodiments, the e-fuse structure includes: a substrate; an insulator layer over the substrate; a pair of contact regions overlying the insulator layer; and a silicide channel overlying the insulator layer and connecting the pair of contact regions, the silicide channel having a first portion including silicide silicon and a second portion coupled with the first portion and on a common level with the first portion, the second portion including silicide silicon germanium (SiGe) or silicide silicon phosphorous (SiP).