Patents by Inventor James A. Harnden
James A. Harnden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20120056261Abstract: Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.Type: ApplicationFiled: October 31, 2011Publication date: March 8, 2012Applicant: GEM Services, Inc.Inventors: James Harnden, Lynda Harnden, Anthony Chia, Liming Wong, Hongbo Yang, Anthony C. Tsui, Hui Teng, Ming Zhou
-
Patent number: 8097945Abstract: Embodiments of the present invention relate to an improved die layout for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.Type: GrantFiled: November 21, 2007Date of Patent: January 17, 2012Inventors: James Harnden, Lynda Harnden, legal representative, Anthony Chia, Liming Wong, Hongbo Yang, Anthony C. Tsui, Hui Teng, Ming Zhou
-
Publication number: 20110291254Abstract: Embodiments of the present invention relate to semiconductor device packages featuring encapsulated leadframes in electrical communication with at least one die through electrically conducting bumps or balls and electrically conducting ribbons. Embodiments of the present invention may permit multiple die and/or multiple passive devices to occupy space in the package previously consumed by the diepad. The result is a flexible packaging process allowing the combination of die and technologies required for complete sub-systems in a conventional small JEDEC specified footprint.Type: ApplicationFiled: August 9, 2011Publication date: December 1, 2011Applicant: GEM Services, Inc.Inventors: James Harnden, Richard K. Williams, Anthony Chia, Teng Hui, Hongbo Yang, Zhou Ming, Anthony C. Tsui
-
Patent number: 7667309Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.Type: GrantFiled: March 14, 2008Date of Patent: February 23, 2010Assignee: GEM Services, Inc.Inventors: James Harnden, Allen K. Lam, Richard K. Williams, Anthony Chia, Chu Weibing
-
Publication number: 20090179265Abstract: Embodiments of the present invention relate to an improved die layout for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.Type: ApplicationFiled: November 21, 2007Publication date: July 16, 2009Applicant: GEM Services, Inc.Inventors: James Harnden, Anthony Chia, Liming Wong, Hongbo Yang, Anthony C. Tsui, Hui Teng, Ming Zhou, Lynda Harnden
-
Patent number: 7485498Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.Type: GrantFiled: February 2, 2007Date of Patent: February 3, 2009Assignee: GEM Services, Inc.Inventors: James Harnden, Allen K. Lam, Richard K. Williams, Anthony Chia, Chu Weibing
-
Publication number: 20080217662Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.Type: ApplicationFiled: March 14, 2008Publication date: September 11, 2008Applicant: GEM Services, Inc.Inventors: James Harnden, Allen K. Lam, Richard K. Williams, Anthony Chia, Chu Weibing
-
Publication number: 20080135991Abstract: Embodiments of the present invention relate to semiconductor device packages featuring encapsulated leadframes in electrical communication with a supported die through electrically conducting bumps or balls. By eliminating the need for a separate diepad and lateral isolation between an edge of the diepad and adjacent non-integral leads or pins, embodiments of packages fabricated by bump on leadframe (BOL) processes in accordance with embodiments of the present invention increase the space available to the die for a given package footprint. Embodiments of the present invention may also permit multiple die and/or multiple passive devices to occupy space in the package previously consumed by the diepad. The result is a flexible packaging process allowing the combination of die and technologies required for complete sub-systems in a conventional small JEDEC specified footprint.Type: ApplicationFiled: December 12, 2006Publication date: June 12, 2008Applicant: GEM Services, Inc.Inventors: James Harnden, Richard K. Williams, Anthony Chia, Teng Hui, Hongbo Yang, Zhou Ming, Anthony C. Tsui
-
Publication number: 20080111219Abstract: Embodiments in accordance with the present invention relate to packaging designs for vertical conduction semiconductor devices which include low electrical resistance contacts with a top surface of the die. In one embodiment, the low resistance contact may be established by the use of Aluminum ribbon bonding with one side of a leadframe, or with both of opposite sides of a leadframe. In accordance with a particular embodiment, the vertical conduction device may be housed within a Quad Flat No-lead (QFN) package modified for that purpose.Type: ApplicationFiled: November 14, 2006Publication date: May 15, 2008Applicant: GEM Services, Inc.Inventors: James Harnden, Anthony Chia, Liming Wong, Hongbo Yang
-
Publication number: 20070134851Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.Type: ApplicationFiled: February 2, 2007Publication date: June 14, 2007Applicant: GEM Services, Inc.Inventors: James Harnden, Allen Lam, Richard Williams, Anthony Chia, Chu Weibing
-
Publication number: 20070130759Abstract: A leadframe having raised features for use a semiconductor device package, is fabricated by bonding together at least two metal layers. A first metal layer may define the lateral dimensions of the leadframe, including any diepad and leads. A second metal layer bonded to the first metal layer, may define the raised features of the leadframe, such as steps for physically securing the leadframe within the package body. The multiple metal layers may be bonded together by a number of possible techniques, including but not limited to ultrasonic welding, soft soldering, or the use of epoxy. Prior to or after bonding, one or more of the metal layers may be coined or stamped to form additional features such as offsets or channels.Type: ApplicationFiled: May 2, 2006Publication date: June 14, 2007Applicant: GEM Services, Inc.Inventors: James Harnden, Anthony Chia, Liming Wong, Hongbo Yang
-
Patent number: 7215012Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.Type: GrantFiled: December 12, 2003Date of Patent: May 8, 2007Assignee: GEM services, Inc.Inventors: James Harnden, Allen K. Lam, Richard K. Williams, Anthony Chia, Chu Weibing
-
Publication number: 20070007640Abstract: Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments, packages having leads of a reverse gull wing shape reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body and to the enclosed die. Embodiments of packages in accordance with the present invention may also reduce the package vertical profile by featuring recesses for receiving lead feet ends, thereby reducing clearance between the package bottom and the PC board. Providing a linear lead foot underlying the package and slightly inclined relative to the PC board further reduces vertical package profile by eliminating additional clearance associated with radiuses of curvature of J-shaped leads.Type: ApplicationFiled: September 15, 2006Publication date: January 11, 2007Applicant: GEM Services, Inc.Inventors: James Harnden, Richard Williams, Anthony Chia, Chu Weibing
-
Patent number: 7057273Abstract: Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments, packages having leads of a reverse gull wing shape reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body and to the enclosed die. Embodiments of packages in accordance with the present invention may also reduce the package vertical profile by featuring recesses for receiving lead feet ends, thereby reducing clearance between the package bottom and the PC board. Providing a linear lead foot underlying the package and slightly inclined relative to the PC board further reduces vertical package profile by eliminating additional clearance associated with radiuses of curvature of J-shaped leads.Type: GrantFiled: June 29, 2001Date of Patent: June 6, 2006Assignee: GEM Services, Inc.Inventors: James Harnden, Richard K. Williams, Anthony Chia, Chu Weibing
-
Publication number: 20050145998Abstract: Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments, packages having leads of a reverse gull wing shape reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body and to the enclosed die. Embodiments of packages in accordance with the present invention may also reduce the package vertical profile by featuring recesses for receiving lead feet ends, thereby reducing clearance between the package bottom and the PC board. Providing a linear lead foot underlying the package and slightly inclined relative to the PC board further reduces vertical package profile by eliminating additional clearance associated with radiuses of curvature of J-shaped leads.Type: ApplicationFiled: February 11, 2005Publication date: July 7, 2005Applicant: GEM Services, Inc.Inventors: James Harnden, Richard Williams, Anthony Chia, Chu Weibing
-
Patent number: D513608Type: GrantFiled: January 3, 2003Date of Patent: January 17, 2006Assignee: GEM Services, Inc.Inventors: James Harnden, Richard K. Williams, Anthony Chia, Chu Weibing, Allen K. Lam
-
Patent number: D558694Type: GrantFiled: October 11, 2005Date of Patent: January 1, 2008Assignee: GEM Services, Inc.Inventors: James Harnden, Anthony Chia, Liming Wong, Hongbo Yang
-
Patent number: D560623Type: GrantFiled: October 11, 2005Date of Patent: January 29, 2008Assignee: GEM services, Inc.Inventors: James Harnden, Anthony Chia, Liming Wong, Hongbo Yang
-
Patent number: D588080Type: GrantFiled: September 26, 2007Date of Patent: March 10, 2009Assignee: GEM Services, Inc.Inventors: James Harnden, Anthony Chia, Hongbo Yang, Teng Hui
-
Patent number: D588557Type: GrantFiled: October 2, 2007Date of Patent: March 17, 2009Assignee: GEM Services, Inc.Inventors: James Harnden, Anthony Chia, Hongbo Yang, Teng Hui