Patents by Inventor James M. Derderian

James M. Derderian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170053881
    Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.
    Type: Application
    Filed: November 7, 2016
    Publication date: February 23, 2017
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: JASPREET S. GANDHI, JAMES M. DERDERIAN, SAMEER S. VADHAVKAR, JIAN LI
  • Publication number: 20160372452
    Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.
    Type: Application
    Filed: September 1, 2016
    Publication date: December 22, 2016
    Inventors: Sameer S. Vadhavkar, Xiao Li, Steven K. Groothuis, Jian Li, Jaspreet S. Gandhi, James M. Derderian, David R. Hembree
  • Patent number: 9515002
    Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: December 6, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Jaspreet S Gandhi, James M. Derderian, Sameer S Vadhavkar, Jian Li
  • Publication number: 20160343687
    Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.
    Type: Application
    Filed: May 19, 2015
    Publication date: November 24, 2016
    Inventors: Sameer S. Vadhavkar, Jaspreet S. Gandhi, James M. Derderian
  • Publication number: 20160343689
    Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.
    Type: Application
    Filed: August 5, 2016
    Publication date: November 24, 2016
    Inventors: Jaspreet S. Gandhi, Wayne H. Huang, James M. Derderian
  • Patent number: 9443744
    Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: September 13, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Xiao Li, Steven K. Groothuis, Jian Li, Jaspreet S. Gandhi, James M. Derderian, David R. Hembree
  • Publication number: 20160233139
    Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.
    Type: Application
    Filed: February 9, 2015
    Publication date: August 11, 2016
    Inventors: JASPREET S. GANDHI, JAMES M. DERDERIAN, SAMEER S. VADHAVKAR, JIAN LI
  • Patent number: 9412675
    Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: August 9, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Jaspreet S. Gandhi, Wayne H. Huang, James M. Derderian
  • Publication number: 20160084905
    Abstract: Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 24, 2016
    Inventors: Jaspreet S. Gandhi, Michel Koopmans, James M. Derderian
  • Publication number: 20160013115
    Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.
    Type: Application
    Filed: July 14, 2014
    Publication date: January 14, 2016
    Inventors: Sameer S. Vadhavkar, Xiao Li, Steven K. Groothuis, Jian Li, Jaspreet S. Gandhi, James M. Derderian, David R. Hembree
  • Publication number: 20160013173
    Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
    Type: Application
    Filed: July 14, 2014
    Publication date: January 14, 2016
    Inventors: Sameer S. Vadhavkar, Xiao Li, Steven K. Groothuis, Jian Li, Jaspreet S. Gandhi, James M. Derderian, David R. Hembree
  • Publication number: 20150333026
    Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.
    Type: Application
    Filed: May 19, 2014
    Publication date: November 19, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Jaspreet S. Gandhi, Wayne H. Huang, James M. Derderian
  • Patent number: 8101459
    Abstract: A method for assembling semiconductor devices includes providing a first semiconductor device, securing spacers to noncircuit bond pads of the first semiconductor device, and positioning a second semiconductor device on the spacers. Adhesive material may be applied to a surface of one or both of the first and second semiconductor devices prior to positioning of the second semiconductor device, or introduced between first and second semiconductor devices. The noncircuit bond pads may be electrically isolated from other structures of the first semiconductor device or communicate with a ground or reference voltage plane, in which case the back side of the second semiconductor device may communicate with the ground or reference voltage plane upon being positioned against the spacers. Additional semiconductor devices may be added to the assembly. The first semiconductor device may be associated with a substrate. Assemblies and packages at least partially fabricated by the method are also disclosed.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: January 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: James M. Derderian
  • Patent number: 7858420
    Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of singulated imaging dies to a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes forming a plurality of stand-offs on corresponding imaging dies before and/or after the imaging dies are singulated and electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member. The individual stand-offs include a portion between adjacent external contacts.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: December 28, 2010
    Assignee: Micron Technology, Inc.
    Inventors: James M. Derderian, Bret K. Street, Eric T. Mueller
  • Patent number: 7786574
    Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes attaching a plurality of covers to corresponding imaging dies, cutting the microfeature workpiece to singulate the imaging dies, and coupling the singulated dies to a support member. The covers can be attached to the imaging dies before or after the workpiece is cut.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: August 31, 2010
    Assignee: Aptina Imaging Corp.
    Inventors: James M. Derderian, Bret K. Street, Eric T. Mueller
  • Publication number: 20100167451
    Abstract: Methods of manufacturing an imaging device package are provided. In accordance with an embodiment a sensor die may be coupled to bond pads on a transparent substrate. Electrically conductive paths comprising bond wires are formed through the bond pads from the sensor die to an outer surface of the imaging device package.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 1, 2010
    Applicant: Micron Technology, Inc.
    Inventor: James M. Derderian
  • Patent number: 7691660
    Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes attaching a plurality of covers to corresponding imaging dies, cutting the microfeature workpiece to singulate the imaging dies, and coupling the singulated dies to a support member. The covers can be attached to the imaging dies before or after the workpiece is cut.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: April 6, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: James M. Derderian, Bret K. Street, Eric T. Mueller
  • Patent number: 7675131
    Abstract: There is provided an imager package including an image sensor die attached to a transparent substrate such that sensitive image sensing components on the sensor die face the transparent substrate. In accordance with an embodiment of the present technique, the imager package may be coupled to an external package via bond wires and other interconnect elements. The sensor die and bond wires may be protected by an encapsulant on which the interconnect elements may be disposed. The bond wires may enable placement of the interconnect elements partially or directly above the sensor die, as opposed to around an outer periphery of the sensor die. There is further provided a method of manufacturing an imager package wherein interconnect elements may be located partially or directly above the sensor die, enabling the manufacture of smaller imager packages than previously envisioned.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: March 9, 2010
    Assignee: Micron Technology, Inc.
    Inventor: James M. Derderian
  • Patent number: 7655507
    Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of singulated imaging dies to a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes forming a plurality of stand-offs on corresponding imaging dies before and/or after the imaging dies are singulated and electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member. The individual stand-offs include a portion between adjacent external contacts.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: February 2, 2010
    Assignee: Micron Technology Inc.
    Inventors: James M. Derderian, Bret K. Street, Eric T. Mueller
  • Publication number: 20090243012
    Abstract: A microelectronic device assembly with an integrated conductive shield is disclosed herein. The microelectronic device assembly includes a semiconductor substrate, an integrated circuit carried by the semiconductor substrate, a dielectric encapsulant encasing at least a portion of the semiconductor substrate. The microelectronic device assembly also includes a conductive shield in direct contact with at least a portion of the dielectric encapsulant and an interconnect extending through the semiconductor substrate and in direct contact with the conductive shield.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kiran Kumar Vanam, Derek J. Gochnour, Alan G. Wood, James M. Derderian, Luke G. England, Owen R. Fay