Abstract: Microelectronic device assemblies having integrated conductive shields are disclosed herein. The microelectronic device assemblies include a semiconductor substrate having a bond site and a solder ball electrically connected to the bond site, a dielectric sidewall at least partially encapsulating the semiconductor substrate, and a conductive shield in direct contact with the sidewall and in electrical communication with the solder ball and the bond site.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes attaching a plurality of covers to corresponding imaging dies, cutting the microfeature workpiece to singulate the imaging dies, and coupling the singulated dies to a support member. The covers can be attached to the imaging dies before or after the workpiece is cut.

Abstract: A semiconductor device that includes at least one nonconfluent spacer layer on at least one surface thereof. The at least one nonconfluent spacer layer at least partially spaces the surface of the semiconductor device apart from another semiconductor device assembled in stacked arrangement therewith. Adjacent stacked semiconductor devices may include abutting nonconfluent spacer layers which together define a distance between opposed surfaces of the semiconductor devices. Each nonconfluent spacer layer includes voids therein that communicate with an exterior periphery of the layer to facilitate the lateral introduction of adhesive or encapsulant material into the layer and between the adjacent, stacked semiconductor devices. Multi-chip modules are also disclosed, as are methods for forming the nonconfluent spacer layers and assembly and packaging methods.

Abstract: Microelectronic imaging units having covered image sensors are disclosed herein. In one embodiment, the microelectronic imaging units have an image sensor, an integrated circuit, a cover located over the image sensor, at least one dam, and a fill material between adjacent imaging units. The covers may be located on discrete adhesive portions inboard of external contacts that are operably coupled to the integrated circuits.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method for manufacturing a plurality of microelectronic imaging units includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include a first height, an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member and forming a base on the support member between adjacent imaging dies. The base has a second height less than or approximately equal to the first height of the dies. The method further includes attaching a plurality of covers to the base so that the covers are positioned over corresponding image sensors.

Abstract: A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element. A second embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches that extend from one edge of the transparent element to the other edge. A third embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches. A fourth embodiment has a transparent element with an adhesive flow restriction area formed as a protuberance. A fifth embodiment comprises a trench in the die. A sixth embodiment has a die with a plurality of trenches in the die as an adhesive flow restriction area. A seventh embodiment has a die with a protuberance.

Abstract: A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element. A second embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches that extend from one edge of the transparent element to the other edge. A third embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches. A fourth embodiment has a transparent element with an adhesive flow restriction area formed as a protuberance. A fifth embodiment comprises a trench in the die. A sixth embodiment has a die with a plurality of trenches in the die as an adhesive flow restriction area. A seventh embodiment has a die with a protuberance.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of singulated imaging dies to a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes forming a plurality of stand-offs on corresponding imaging dies before and/or after the imaging dies are singulated and electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member. The individual stand-offs include a portion between adjacent external contacts.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of singulated imaging dies to a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes forming a plurality of stand-offs on corresponding imaging dies before and/or after the imaging dies are singulated and electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member. The individual stand-offs include a portion between adjacent external contacts.

Abstract: There is provided an imager package including an image sensor die attached to a transparent substrate such that sensitive image sensing components on the sensor die face the transparent substrate. In accordance with an embodiment of the present technique, the imager package may be coupled to an external package via bond wires and other interconnect elements. The sensor die and bond wires may be protected by an encapsulant on which the interconnect elements may be disposed. The bond wires may enable placement of the interconnect elements partially or directly above the sensor die, as opposed to around an outer periphery of the sensor die. There is further provided a method of manufacturing an imager package wherein interconnect elements may be located partially or directly above the sensor die, enabling the manufacture of smaller imager packages than previously envisioned.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of singulated imaging dies to a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes forming a plurality of stand-offs on corresponding imaging dies before and/or after the imaging dies are singulated and electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member. The individual stand-offs include a portion between adjacent external contacts.

Abstract: A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over a back side of the wafer while in a rough state from backgrinding without prior, conventional polishing or plasma etching of the back side. The thin layer or film of reinforcement material fills grooves, fractures and scratches in the back side of the wafer, enhances the rigidity of the wafer and provides a planar, smooth, back side surface layer. The reinforcement material counteracts internal stresses of the wafer tending to warp, crack and propagate lattice defects in the wafer. The reinforcement material may also be configured to act as a die attach adhesive, may provide an ionic barrier, and may remain as part of the packaging for semiconductor dice singulated from the wafer.

Abstract: Microelectronic imaging units and methods for manufacturing microelectronic imaging units are disclosed herein. In one embodiment, a method includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes disposing a plurality of discrete stand-offs on the support member. The discrete stand-offs are arranged in arrays relative to corresponding imaging dies. The method further includes electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member, and attaching a plurality of covers to corresponding stand-off arrays so that the covers are positioned over the image sensors.

Abstract: Microelectronic imaging units and methods for manufacturing microelectronic imaging units are disclosed herein. In one embodiment, a method includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes disposing a plurality of discrete stand-offs on the support member. The discrete stand-offs are arranged in arrays relative to corresponding imaging dies. The method further includes electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member, and attaching a plurality of covers to corresponding stand-off arrays so that the covers are positioned over the image sensors.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of singulated imaging dies to a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes forming a plurality of stand-offs on corresponding imaging dies before and/or after the imaging dies are singulated and electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member. The individual stand-offs include a portion between adjacent external contacts.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method for manufacturing a plurality of microelectronic imaging units includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include a first height, an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member and forming a base on the support member between adjacent imaging dies. The base has a second height less than or approximately equal to the first height of the dies. The method further includes attaching a plurality of covers to the base so that the covers are positioned over corresponding image sensors.

Abstract: A method for assembling semiconductor devices includes providing a first semiconductor device, applying a predetermined volume of adhesive material to at least a surface of the first semiconductor device, and positioning a second semiconductor device adjacent to the first semiconductor device in superimposed relation thereto. The adhesive material may be applied to a surface of the first semiconductor device prior to positioning the second semiconductor device thereover, or introduced between the first and second semiconductor devices. Upon curing or hardening, the predetermined volume of adhesive material spaces the first and second semiconductor devices a predetermined distance apart from one another. Additional semiconductor devices may also be added to the assembly. The first semiconductor device may be associated with a substrate. Semiconductor device assemblies and packages that are at least partially fabricated in accordance with the method are also disclosed.

Abstract: A method for assembling semiconductor devices includes providing a first semiconductor device, applying a volume of adhesive material to at least a surface of the first semiconductor device, and positioning a second semiconductor device over the first semiconductor device and a portion of at least one discrete conductive element protruding thereabove. The adhesive material may be applied to a surface of the first semiconductor device prior to positioning the second semiconductor device thereover, or introduced between the first and second semiconductor devices. Upon curing, the predetermined volume of adhesive material spaces the first and second semiconductor devices a predetermined distance apart from one another. Additional semiconductor devices may also be added to the assembly. The first semiconductor device may be associated with a substrate. Semiconductor device assemblies and packages that are at least partially fabricated in accordance with the method are also disclosed.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes attaching a plurality of covers to corresponding imaging dies, cutting the microfeature workpiece to singulate the imaging dies, and coupling the singulated dies to a support member. The covers can be attached to the imaging dies before or after the workpiece is cut.

Abstract: A method and intermediate structure for improving the thinning and planarity of a wafer back side utilizing planarization material applied to the back side prior to at least one portion of the thinning operation and which is subsequently removed concurrently with the wafer material by one or more suitable thinning or planarization techniques. The planarization material may be applied as a thin layer or film of a hardenable material to the rough, bare back side of a wafer to produce a planar surface when hardened. The planarization material is selected to exhibit a material removal rate approximating the removal rate of the wafer material for a given removal technique such as etching, mechanical abrasion or chemical-mechanical planarization (CMP). This approach to wafer thinning and planarization results in improved process control in the form of uniform material removal rates, reduction in wafer warpage, final surface smoothness and planarity, and even distribution of residual stresses.