Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

Abstract: Apparatus and systems, as well as methods and articles, may operate to provide a majority voter indication using a sense amplifier coupled to a first plurality of bit inputs and to a second plurality of bit inputs.

Abstract: A bias generator unit is provided that includes a central bias generator to provide a bias voltage, a local bias generator to receive the bias voltage and a reference voltage and to provide a forward body bias signal or a reverse body bias signal. The bias generator may include a charge pump to output (or provide) a reference voltage to a reference generator, which in turn provides reference signals to the central bias generator. As a result, the local bias generator may control the body bias signal provided by the local bias generator.

Abstract: An approach for power reduction of an integrated circuit device. In response to detecting a change in an activity factor associated with an integrated circuit device from a first activity factor to a second activity factor, a supply voltage and a body bias associated with the integrated circuit device are adjusted based on the second activity factor to reduce power consumption. For one aspect, the supply voltage and body bias are adjusted to maintain a substantially constant operating frequency for the integrated circuit device.

Abstract: Some embodiments provide reception of a clock signal, reception of a gating signal, and output of a gated clock signal to a dual edge-triggered-clocked circuit. The gated clock signal is based on the clock signal and on the gating signal.

Abstract: Apparatuses and methods for delaying thermal throttling of processor devices by decreasing threshold voltages are disclosed.

Abstract: A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.

Abstract: In some embodiments, a method includes providing an integrated circuit (IC) die in a package. The IC die may have a metal layer on a back surface of the IC die. The method may also include applying a bias signal to the IC die via the metal layer.

Abstract: An apparatus for and method of modifying an IC design layout of an integrated circuit, comprising: accessing an initial IC design layout, with the initial layout including a plurality of MOSFET devices having a common substrate; and removing a plurality of body contacts of the MOSFET devices to create a first modified IC design layout.

Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.

Abstract: Transistor bodies are biased to modify delay in clock buffers.

Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract: Embodiments circuits provide a transistor body bias voltage so that the ratio of ION to IOFF is constant over a range of temperature, where ION is a transistor current when ON and IOFF is a (leakage) transistor current when OFF. In one embodiment, a nFET is biased to provide ION to a current mirror that sources a current AION to a node, a nFET is biased to provide IOFF to a current mirror that sinks a current BIOFF from the node, and an amplifier provides feedback from the node to the body terminals of the nFETs so that at steady state AION=BIOFF, where A and B are constants independent over a range of temperature. In this way, the ratio ION/IOFF is maintained at B/A for some range of temperatures. Other embodiments are described and claimed.

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract: A circuit is provided having a differential difference amplifier (DDA) having first and second inputs to receive a desired body bias signal, and a third input to receive a supply voltage, the DDA configured to generate an intermediate output signal, the intermediate output signal coupled to an output buffer generating an output signal having a desired gain, the DDA having a fourth input, to cause the output signal to reference to variations in the supply voltage.

Abstract: According to some embodiments, provided are a first signal line, the first signal line coupled to a first repeater, the first repeater to convert a first signal from a received signal level to an output signal level, the first repeater to convert from a first signal level to a second signal level slower than from the second signal level to the first signal level, and a second signal line adjacent to the first signal line, the second signal line coupled to a second repeater adjacent to the first repeater, the second repeater to convert a second signal from a second received signal level to a second output signal level, the second repeater to convert from the first signal level to the second signal level slower than from the second signal level to the first signal level, wherein the received signal level is substantially equivalent to the second output signal level and wherein the second received signal level is substantially equivalent to the output signal level.

Abstract: A logic unit and method incorporating body biasing using scan chains, the logic unit comprising a functional unit block including a body and a scan chain, and a variable voltage source coupled to the scan chain to receive control signals from the scan chain and coupled to the body to provide a bias voltage to the body, and the method comprising identifying a preferred body bias voltage for a functional unit block having a body; and permanently programming a plurality of control signals coupled to a variable voltage source that provides the preferred body bias voltage to the body.

Abstract: A method and apparatus for bus repeater tapering. The sizing of repeaters on a portion of one transmission line is chosen to propagate a signal transition at a particular rate. The sizing of repeaters on a substantially parallel portion of another transmission line, is chosen to propagate a second signal transition at a different rate. Thus, the worst-case capacitance coupling factor between the two transmission lines may be reduced.