Abstract: According to some embodiments, provided are a first signal line, the first signal line coupled to a first repeater, the first repeater to convert a first signal from a received signal level to an output signal level, the first repeater to convert from a first signal level to a second signal level slower than from the second signal level to the first signal level, and a second signal line adjacent to the first signal line, the second signal line coupled to a second repeater adjacent to the first repeater, the second repeater to convert a second signal from a second received signal level to a second output signal level, the second repeater to convert from the first signal level to the second signal level slower than from the second signal level to the first signal level, wherein the received signal level is substantially equivalent to the second output signal level and wherein the second received signal level is substantially equivalent to the output signal level.

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract: An approach for power reduction of an integrated circuit device. In response to detecting a change in an activity factor associated with an integrated circuit device from a first activity factor to a second activity factor, a supply voltage and a body bias associated with the integrated circuit device are adjusted based on the second activity factor to reduce power consumption. For one aspect, the supply voltage and body bias are adjusted to maintain a substantially constant operating frequency for the integrated circuit device.

Abstract: A system and method to reduce leakage power while minimizing performance penalties and noise is disclosed. In accordance with one embodiment of the invention, the system includes at least one sleep transistor operatively coupleable between a system power supply and at least one circuit powered by the system power supply to control the application of power to the circuit. The sleep transistor is also operatively coupleable to receive a sleep control signal to turn the sleep transistor on and off. A body bias voltage generator is operatively coupleable to a body of the at least one sleep transistor to substantially reduce leakage current when the sleep transistor is non-operational or idle and to improve the operational characteristics of the sleep transistor when the transistor is operational by reducing the performance penalty of the sleep transistor and by reducing impact of noise on the circuit and other devices.

Abstract: According to some embodiments, a wide-range local bias generator provides a body bias voltage to transistors in an integrated circuit.

Abstract: Flip-flop circuitry having an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal; a clock terminal configured to provide timing signals for reception of the input signal at the input and transmission of the output signal at the output; two on-path inverters connected serially between the input and output, and configured not to respond to the timing signals; and two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signals.

Abstract: A method is provided for designing an electronic device. This may include determining a capacitance ratio of a design of the electronic device and altering the design so as to increase the capacitance ratio of said electronic device. The capacitance ratio may be Cdj/(Cdj+Csj+CBOX), where Cdj is a capacitance of a drain-body junction, Csj is a capacitance of a source-body junction and CBOX is a capacitance of a buried oxide layer.

Abstract: A pulse generator system includes a plurality of buffers at least two transmission gates. The inverters successively and input insert delays into an signal having a series of pulses, each pulse having first and second edges. The transmission gates are operatively coupled to the inverters. The first transmission gate selectively passes the input signal. The second transmission gape selectively passes inverted signal of the input signal.

Abstract: Flip-flop circuitry having an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal; a clock terminal configured to provide timing signals for reception of the input signal at the input and transmission of the output signal at the output; two on-path inverters connected serially between the input and output, and configured not to respond to the timing signals; and two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signals.

Abstract: A method and apparatus for reducing leakage current in an integrated circuit includes a supply voltage line, a virtual supply voltage line, a ground voltage line, a virtual ground voltage line, a first logic circuit coupled to the ground voltage line and selectively coupled to the virtual supply voltage line, a second logic circuit coupled to the supply voltage line and selectively coupled to the virtual ground voltage line, and a switch circuit configured to control the selective coupling of the first logic circuit to the virtual supply line voltage and the second logic circuit to the virtual ground voltage line.

Abstract: A logic unit and method incorporating body biasing using scan chains, the logic unit comprising a functional unit block including a body and a scan chain, and a variable voltage source coupled to the scan chain to receive control signals from the scan chain and coupled to the body to provide a bias voltage to the body, and the method comprising identifying a preferred body bias voltage for a functional unit block having a body; and permanently programming a plurality of control signals coupled to a variable voltage source that provides the preferred body bias voltage to the body.

Abstract: A method and apparatus for transmitting data through a CMOS bus line includes a pulse generator to generate a pulse representing a data signal, and a decoder for receiving the pulse and an output port for delivering the detected signal to a receiving device.

Abstract: A method and apparatus for reducing leakage current in an integrated circuit includes a supply voltage line, a virtual supply voltage line, a ground voltage line, a virtual ground voltage line, a first logic circuit coupled to the ground voltage line and selectively coupled to the virtual supply voltage line, a second logic circuit coupled to the supply voltage line and selectively coupled to the virtual ground voltage line, and a switch circuit configured to control the selective coupling of the first logic circuit to the virtual supply line voltage and the second logic circuit to the virtual ground voltage line.

Abstract: A pulse generator system is disclosed. The system includes a plurality of buffers and at least two transmission gates. The inverters successively insert delays into an input signal having a series of pulses, each pulse having first and second edges. The transmission gates are operatively coupled to the inverters. The first transmission gate selectively passes the input signal. The second transmission gate selectively passes inverted signal of the input signal.

Abstract: A circuit including a data signal input to receive a data signal, a clock signal input to receive a clock signal, a clocking circuit to generate control clocks, and a multiple input conditional inverter to receive the data signal and control clocks, and to generate an output. The circuit also includes at least one stack node pre-charging transistor coupled to a high signal transfer node in the multiple input conditional inverter and at least one stack node pre-discharging transistor coupled to a low signal transfer node in the multiple input conditional inverter. A keeper circuit receives the output of the multiple input conditional inverter and a buffer circuit receives the output of the multiple input conditional inverter and generates the circuit output.