Abstract: A tie cell includes a first flip-flop having a physically unclonable function (PUF), a second flip-flop that generates a PUF key value, and logic that logically combines the PUF value and the PUF key value to generate an output signal having a constant logical value. The PUF value is based on a power-up value stored in the first flip-flop, which power-up value is generated based on physical and/or electrical characteristics produced from a manufacturing process. The output value is generated to tie digital logic to the constant logical value.

Abstract: An integrated circuit device includes an array of read/write memory cells, application logic circuitry, and address decoder circuitry coupled to receive input from the application logic circuitry and to provide output to the array of memory cells. The address decoder circuitry is reversible by having a bijective transfer function from the inputs to the outputs of the address decoder circuitry, and conservative by having the same number of 1's at the input and the output. During a test, the application logic circuitry provides a test value and test ancilla bits to the address decoder circuitry. During normal operation, the application logic circuitry provides an application memory address and constant ancilla bits to the address decoder circuitry.

Abstract: An apparatus comprising: a functional circuit comprising one or more circuit components configured to perform a function based on one or more first input signals; at least one failure-prediction circuit for use in predicting failure of the functional circuit, the failure-prediction circuit comprising a replica of the functional circuit in terms of constituent circuit components; wherein the failure-prediction circuit is configured to be more susceptible to failure than said functional circuit, wherein the apparatus is configured to provide a prediction of failure of the functional circuit based on a determination of failure of the failure-prediction circuit.

Abstract: The disclosure relates to monitoring of feedback systems such as phase lock loops. A system is disclosed, comprising: a feedback circuit (100); and a monitoring module (190). The monitoring module (190) is configured to: i) receive actual values of at least one state variable describing the state of the feedback circuit at a first time; ii) determine a predicted future value of the at least one state variable at a second time from the actual values at the first time using a model of the feedback circuit; iii) receive actual values of the at least one state variable at the second time; iv) compare the predicted future value of the at least one state variable at the second time with the actual value of the at least one state variable at the second time; and v) determine whether the feedback circuit has a fault condition, depending on the results of step iv).

Abstract: An apparatus configured to: receive a digital input signal; receive a processing-direction-signal that can have a forward-value or a backward-value; and provide a digital output signal. The apparatus comprising a processor configured to apply an involutional cryptographic function to the digital input signal by: for a first operation: apply a first step of the involutional cryptographic function to the digital input signal in order to implement a forward calculation to move to the next step in the sequence; and perform a plurality of further operations until the forward calculation of a last step is performed. Each further operation comprises: if the processing-direction-signal has a forward-value: then perform the forward calculation for the current step; or if the processing-direction-signal has a backward-value: then perform a backward calculation for the current step.

Abstract: The disclosure relates to detecting jitter in phase locked loop (PLL) circuits. Embodiments disclosed include a phase-locked loop, PLL (500) comprising: a phase comparison module (201); a loop filter (102); a voltage controller oscillator, VCO (103); a feedback divider (104); and a jitter evaluation module (502), the phase comparison module (201) comprising a phase comparator (202) and a measurement module (204) configured to detect a metastable output in the phase comparator (202) over active clock cycles of application and feedback clock signals (105, 106) input to the phase comparison module (201) and provide an output signal (208) to the jitter evaluation module (502) indicating a metastability resolution time for the phase comparator (202), the jitter evaluation module (210) being configured to provide an output indicative of jitter based on the metastability resolution time.

Abstract: A method for controlling access to a chip includes obtaining first values of a first physically unclonable function of the chip, obtaining second values that correspond to at least one challenge word, performing a simulation based on the first values and the second values, and generating an authentication result for the chip based on results of the simulation. The simulation may generate responses to logical operations corresponding to combinatorial logic in the chip, and the logical operations may be performed based on a predetermined sequence of the first values and the second values. The chip may be authenticated based on a match between the responses generated by the simulation and a second physically unclonable function of the chip.

Abstract: A communications system (300) comprising: an antenna (320) that comprises a plurality of serially connected sub-antenna elements (322); and a signal generator (324) configured to provide a transmission signal to the antenna (320) for propagating along the sub-antenna elements (322). The transmission signal comprises a plurality of serial symbol packets. The signal generator (324) is configured to set the phase of the serial symbol packets such that when they align with predefined ones of the sub-antenna elements (322) the antenna (322) provides a beamformed signal.

Abstract: An apparatus in accordance with embodiments includes front-end radar circuitry and storage circuitry. The front-end radar circuitry generates a digital data stream that represents received radar wave signals and provides a cryptographic hash using the digital data stream, timing information, and apparatus-specific data. The storage circuitry stores the digital data stream and the cryptographic hash indicative of authenticity of the digital data stream.

Abstract: A radar unit (100, 300) is described that comprises: a frequency generation circuit (103, 106, 303, 306) configured to generate a millimetre wave, mmW, frequency modulated continuous wave, FMCW, transmit signal comprising a plurality of chirps; a transmitter circuit (108, 102, 308, 302) configured to transmit the generated mmW FMCW transmit signal: a receiver circuit (104, 110, 304, 310) configured to receive an echo of the mmW FMCW transmit signal; and a built-in self-test, BIST, circuit (140, 340) coupled to the receiver circuit (104, 110, 304, 310) and configured to process the echo of the mmW FMCW transmit signal.

Abstract: A method is provided for detecting a cold boot attack in a data processing system. The data processing system includes a processor, a memory with ECC, and a monitor circuit. In the method, during a boot process of the data processing system, the monitor circuit counts read and write accesses to the memory and maintains a count of the number of errors in the memory detected by the ECC. The read and write access count and the error count are used to detect suspicious activity that may indicate a cold boot attack on the memory. A data processing system that implements the method is also provided.

Abstract: The disclosure relates to a method and system for memory testing to detect memory errors during operation of a memory module. Example embodiments include a method of detecting an error in a memory module (101), the method comprising the sequential steps of: i) receiving (302) a request from a processor executing an application for a read or write operation at a location of the memory module (101) identified by an address; ii) outputting data (304) from, or writing to, the location of the memory module (101); iii) generating (306) by an error detection module (102) a further read request for the location of the memory module (101) identified by the address; iv) receiving (307) at the error detection module (102) an error correction code from the memory module (101) for the location identified by the address; and vi) providing (311) by the error detection module (102) an alert output for the address if the error correction code indicates an error.

Abstract: A method for securing an integrated circuit chip includes obtaining a first value from a first storage area in the chip, obtaining a second value from a second storage area in the chip, generating a third value based on the first value and the second value, and converting a first opcode command obfuscated as a second opcode command into a non-obfuscated form of the first opcode command based on the third value. The first value corresponds to a physically unclonable function (PUF) of the chip. The second value is a key including information indicating a type of obfuscation performed to obfuscate the first opcode command as the second opcode command. The third value may be an inversion flag indicating a type of obfuscation performed to obfuscate the first opcode command as the second opcode command.

Abstract: A method and data processing system is provided for detecting an attack on a physically unclonable function (PUF). In the method, a first list of PUF responses to challenges is produced during production testing of an integrated circuit comprising the PUF. The first list is stored in a memory on the integrated circuit. A second list of PUF responses to the challenges is produced during normal operation of the integrated circuit in the field. The second list is compared to the first list. A difference between entries of the first and second lists computed. If the difference is greater than a threshold difference, then an indication of a hardware trojan is generated. The method may also include monitoring a series of challenges for an indication of a non-random pattern in the series. Detection of a non-random pattern may indicate a modeling attack.

Abstract: The disclosure relates to a data transmission interface for use in a first integrated circuit (IC) for encoding and sending a data packet from the first IC to a second IC via a data bus having four data wires, the data transmission interface arranged to generate four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined four consecutive time stamps T1 . . . T4 at which edges can occur in the signals, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein: irrespective of the data packet content, at each time stamp T1 . . . T4 at least one of the four signals has an edge to enable clock recovery at the second IC.

Abstract: A data transmission interface for use in a first integrated circuit, for encoding and sending a data packet from the first IC to a second IC via a data bus having three data wires, the data transmission interface being arranged to generate three time-dependent binary signals which jointly encode the data packet, each of the signals being associated with a unique data wire of the data bus and spanning a temporal cycle T within which are defined six consecutive time stamps T1 . . . T6 at which the signals are allowed to change logical state, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein, irrespective of the data packet content: at each time stamp T1 . . .

Abstract: One specific example involves an integrated circuit that has application logic circuitry which includes flip-flop circuits susceptible to degradations of setup and hold times relative to specified minimum setup and hold times for signals to be processed by the respective flip-flop circuits. In a method carried out by the integrated circuit, timing-based logic states of the flip-flop circuits are controlled, based on at least one transition-scan pattern processed by the flip-flop circuits as part of the application logic circuitry; and respective logic states are set for those flip-flops, which due to degradations of the actual setup and hold times do not satisfy anymore the originally specified minimum setup and hold times.

Abstract: A method for high data rate transmission using minimum energy coding with Ultra Wide Band modulation includes encoding each of a plurality of sourcewords into a respective codeword. Each respective codeword includes a single logic-high bit. A codeword duty cycle is less than a low duty cycle threshold, wherein the codeword duty cycle is based on a bit length of the codeword. Each respective codeword is modulated with an On-Off-Keying (OOK) modulation to form a respective modulated codeword, wherein a transmission of each modulated codeword occurs only for the single logic-high bit in each respective codeword.

Abstract: A method is provided for detecting a cold boot attack in a data processing system. The data processing system includes a processor, a memory with ECC, and a monitor circuit. In the method, during a boot process of the data processing system, the monitor circuit counts read and write accesses to the memory and maintains a count of the number of errors in the memory detected by the ECC. The read and write access count and the error count are used to detect suspicious activity that may indicate a cold boot attack on the memory. A data processing system that implements the method is also provided.

Abstract: A method for high data rate transmission using minimum energy coding with Ultra Wide Band modulation includes encoding each of a plurality of sourcewords into a respective codeword. Each respective codeword includes a single logic-high bit. A codeword duty cycle is less than a low duty cycle threshold, wherein the codeword duty cycle is based on a bit length of the codeword. Each respective codeword is modulated with an On-Off-Keying (OOK) modulation to form a respective modulated codeword, wherein a transmission of each modulated codeword occurs only for the single logic-high bit in each respective codeword.