Abstract: Embodiments in accordance with the present disclosure are directed to a self-test apparatus for use in an electronic system. The self-test apparatus includes an inter-chip communication bus, a plurality of circuit devices, circuitry including memory, and test controller circuitry. The plurality of circuit devices each has a distributed self-test controller circuit and analog, mixed signal or digital circuit elements. The distributed self-test controller circuits are integrated communicatively via the inter-chip communication bus and negotiate a self-test protocol with each other. The circuitry including memory stores self-test properties of the circuit elements, the self-test properties corresponding to an identifier of each of the circuit elements and a manner or protocol in which the circuit elements are tested.

Abstract: A method is provided for detecting an attack on a keyless entry system for a vehicle. The method includes receiving a wireless transmission by the keyless entry system. The wireless transmission is filtered in a first filter to produce a filtered wireless transmission. The wireless transmission is filtered in a second filter to produce a reference filtered wireless transmission. A frequency band of the filtered wireless transmission is compared to a frequency band of the reference filtered wireless transmission. Based on the comparison, it is determined if the wireless transmission is from a key fob that complies with the specification of the wireless transmission. In another embodiment, a wireless receiver is provided for performing the method.

Abstract: A method of detecting faults in a register bank is disclosed. The register bank includes at least one chain of registers. The method comprises sequentially shifting parameters stored in each register of the chain to an output node of the chain and inverting each parameter and feeding each parameter back to an input node of that chain, and sequentially shifting the inverted parameters through the chain until all the non-inverted parameters have been output at the output node. A first checksum of the parameters output at the output node is calculated. The inverted parameters in each register of the chain are sequentially shifted to the output node of the chain. A second checksum of the inverted parameters output at the output node is calculated, and the first and second checksums are compared.

Abstract: An apparatus includes a linear analog circuit and data-check circuit. The linear analog circuit receives analog input signals and provides processed analog output signals. The linear analog circuit includes voltage-changing and voltage-impedance circuitry that perform processing of the analog input signals by the linear analog circuit and an analog test bus circuit (ATB) that selectively passes different ones of a plurality of input ports to at least one output port. A data-check circuit is communicatively coupled to the ATB and includes a data-processing circuit that detects an error conveyed by the linear analog circuit by applying a control signal, while the linear analog circuit and the data-check circuit facilitate testing of the linear analog circuit, to cause the ATB to selectively pass the different ones of the plurality of input ports.

Abstract: An example analog-test-bus (ATB) apparatus includes a plurality of comparator circuits, each having an output port, and a pair of input ports of opposing polarity including an inverting port and a non-inverting port, a plurality of circuit nodes to be selectively connected to the input ports of a first polarity, and at least one digital-to-analog converter (DAC) to drive the input ports of the plurality of comparator circuits. The apparatus further includes data storage and logic circuitry that accounts for inaccuracies attributable to the plurality of comparator circuits by providing, for each comparator circuit, a set of calibration data indicative of the inaccuracies for adjusting comparison operations performed by the plurality of comparator circuits.

Abstract: An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.

Abstract: A method is provided for authenticating a transceiver in a keyless entry system for a vehicle. The method uses a collision avoidance radar system on the vehicle for authenticating a key fob radar transceiver. A lower power radar signal is transmitted from the vehicle. The lower power radar signal is transmitted below an ambient noise level to make the radar signal difficult for an attacker to detect. The key fob transceiver is then authenticated as being a legitimate transceiver for accessing the vehicle using the low power radar signal. A distance bounding scheme may be used to determine if the key fob is within a predetermined distance. Challenge/response communications may be used to authenticate that the key fob is the legitimate key fob.

Abstract: Embodiments are directed to apparatuses and methods involving communication between a first circuit and a second circuit over a wired-data bus. An example apparatus includes an integrated circuit (IC) chip within one of the first and second circuits and a logic circuit. The IC has a first data-communication port and a second data-communication for connection to respective first and second conductors of the wired-data bus. The logic circuit communicates a code multi-bit word out of a set of code multi-bit words over the wired-data bus by using signal transitions communicated on the first and second conductors. The code multi-bit word conveys clocked data bits indicated by the signal transitions, and information unique relative to other ones of the set of code multi-bit words by a known sequential pattern of the signal transitions defined relative to timing associated with the clocked data bits.

Abstract: An example apparatus includes application circuit that carries out a specific set of actions on an input data vector, and a decoding circuit. The application circuit includes: a first diversification logic circuit that processes data corresponding to the input data vector and in response, generates a coded first output data vector; and a second diversification logic circuit that processes the data corresponding to the input data vector and in response, generate a coded second output data vector, the coded second output data vector being uniquely coded relative to the coded first output data vector. The decoding circuit assesses the coded first output data vector relative to the coded second output data vector and, in response, generates output data indicative of a likelihood of a design weakness in the application circuit.

Abstract: An example method includes stressing, under different circuit-stress test conditions, a plurality of different types of regional circuits susceptible to time dependent dielectric breakdown (TDDB), and in response, monitoring for levels of reliability failure associated with the plurality of different types of regional circuits. The method includes storing a set of stress-test data based on each of the levels of reliability failure, the set of stress-test data being stored within the integrated circuit to indicate reliability-threshold test data specific to the integrated circuit. Within the integrated circuit, an on-chip monitoring circuit indicates operational conditions of suspect reliability associated with dielectric breakdown of at least one of the plurality of different types of regional circuits.

Abstract: A method is provided for detecting an attack on a keyless entry system for a vehicle. The method includes receiving a wireless transmission by the keyless entry system. The wireless transmission is filtered in a first filter to produce a filtered wireless transmission. The wireless transmission is filtered in a second filter to produce a reference filtered wireless transmission. A frequency band of the filtered wireless transmission is compared to a frequency band of the reference filtered wireless transmission. Based on the comparison, it is determined if the wireless transmission is from a key fob that complies with the specification of the wireless transmission. In another embodiment, a wireless receiver is provided for performing the method.

Abstract: A method includes generating a target map indicative of objects around the vehicle using sensor data from sensor circuitry of the vehicle, the sensor circuitry including at least one radar sensor; and determining, by processing circuitry, if the vehicle is being towed away. Determining if the vehicle is being towed away can include comparing the target map to a previously obtained target map, determining if the vehicle is moving based on the comparison, and in response to determining the vehicle is moving, outputting an alarm message indicative of the vehicle being towed away.

Abstract: A method is provided for authenticating a transceiver in a keyless entry system for a vehicle. The method uses a collision avoidance radar system on the vehicle for authenticating a key fob radar transceiver. A lower power radar signal is transmitted from the vehicle. The lower power radar signal is transmitted below an ambient noise level to make the radar signal difficult for an attacker to detect. The key fob transceiver is then authenticated as being a legitimate transceiver for accessing the vehicle using the low power radar signal. A distance bounding scheme may be used to determine if the key fob is within a predetermined distance. Challenge/response communications may be used to authenticate that the key fob is the legitimate key fob.

Abstract: An apparatus embodiment includes a voltage regulator circuit that provides a regulated voltage supply signal, logic state circuitry, test control circuitry, and a supply-signal monitoring circuit. The logic state circuitry includes logic modules that are reconfigured between application controlled self-test modes in which data is shifted through the logic module and while being powered from the regulated voltage supply signal. The test control circuitry operates the controlled self-test mode by causing a predetermined set of the data to shift through the logic modules and that causes the logic state circuitry to load the voltage regulator circuit by stressing the voltage regulator circuit. The supply-signal monitoring circuit monitors a quality parameter of the regulated voltage supply signal and provides an indication of characteristics of the regulated voltage supply signal which bear on a likelihood that the voltage regulator circuit is associated with defective circuitry.

Abstract: Certain aspects of the disclosure are directed to methods and apparatuses of intrusion detection for integrated circuits. An example apparatus can include a wired communications bus configured and arranged to carry data and a plurality of integrated circuits. The plurality of integrated circuits can include a first integrated circuit configured and arranged to operate in a scan mode during which the first integrated circuit performs a scan test to detect one or more faults in circuitry of the plurality of integrated circuits. The plurality of integrated circuits can further include a second integrated circuit configured and arranged to operate in a mission mode and supervise data traffic by monitoring communications including data patterns and accesses on the wired communications bus. In response to identifying a suspected illegitimate access, the second integrated circuit can perform a security action to mitigate a suspect illegitimate action in the plurality of integrated circuits.

Abstract: A dynamic comparator includes two sets of input transistors of opposite conductivity types, where a control electrode of one transistor of each set is coupled to a first input of the comparator and a control input of a second transistor of each set is coupled to a second input of the comparator. The comparator includes bypass transistors for pulling current electrodes of either the first set or second set of input transistors to a power supply terminal depending which input voltage is higher as determined by the output.

Abstract: A method for detecting defeat devices in an engine control unit (ECU) includes storing with a key-data collection unit, a first key-data determined during an environmental test of a vehicle. The key-data collection unit stores a second key-data determined before the environmental test. Wherein, one of the first key-data is determined by the ECU modified by a characteristic only present before the environmental test and the second key-data is determined by the ECU modified by a characteristic only present during the environmental test. An environmental testing device compares the first key-data with the second key-data to detect an anomaly, wherein the anomaly indicates the presence of the defeat device in the ECU.

Abstract: A method and device for detecting a malicious circuit on an integrated circuit (IC) device is provided. The method includes generating a plurality of test patterns on the IC. A scan test circuit and the plurality of test patterns are used to test don't care bits of a function under test on the integrated circuit. Scan out data from the scan test circuit is provided in response to the plurality of test patterns. The scan out data is stored in a memory on the integrated circuit. The scan out data is monitored over a predetermined time period. If it is determined that a characteristic of the scan out data has changed within the predetermined time period, an indication that a malicious circuit has been detected is output. The device includes circuitry for performing the method in the field.

Abstract: A method for triggering and detecting a malicious circuit on an integrated circuit device is provided. A first run of test patterns is provided to logic circuits on the integrated circuit device. Each test pattern of the first run of test patterns includes a plurality of bits, a first portion of the plurality of bits being bits that do not influence a value of a resulting first test output vector, and a second portion of the plurality of bits being bits that will influence the value of the first test output vector. The value of the first test output vector is compared to first expected values. Bit values of the first portion of the plurality of bits for each test pattern of the first run of test patterns are changed to generate a second run of test patterns. The second run of test patterns is provided to the logic circuits on the integrated circuit device. A value of the second run of test patterns is compared to second expected values.

Abstract: A method embodiment includes combining a control signal of a voltage regulator circuit of an apparatus with pseudo-random noise, and using the control signal to provide an output voltage signal as attenuated by a power supply rejection ratio (PSRR) of an analog mixed-signal (AMS) circuit of the apparatus. The method further includes self-testing the AMS circuit by cross-correlating a signal indicative of the output voltage signal from the AMS circuit with the pseudo-random noise and, in response, assessing the results of the cross-correlation relative to a known threshold indicative of a performance level of the AMS circuit.