Abstract: Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit.

Abstract: Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In certain disclosed embodiments, methods for diagnosing faults from compressed test responses are provided. For example, in one exemplary embodiment, a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test is received. A transformation function performed by the compactor to the test responses captured in the circuit-under-test is determined. A diagnostic procedure for evaluating uncompressed test responses is modified into a modified diagnostic procedure that incorporates the transformation function therein. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided.

Abstract: Exemplary embodiments of a compactor for compacting test responses are disclosed. In certain embodiments, the compactor comprises circular registers and has multiple inputs. The circular registers can have lengths that are relatively prime or prime. In certain implementations, the compactors are able to detect errors commonly observed from real defects, such as errors of small multiplicity and burst errors. Certain embodiments of the compactor operate according to modular arithmetic. Furthermore, because circular registers do not multiply errors or unknown states, embodiments of the disclosed compactors can tolerate one or more unknown states or at least exhibit a desirably high tolerance of such states.

Abstract: Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e.g., parallel) over a network of plurality of processors. The network comprises a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Dependent algorithms, or portions thereof, can be performed on the controlling processor or one of the controlled processors in a sequential manner. To ensure consistency between the performance of algorithms, or portions thereof, in a distributed manner and a non-distributed manner, the order of processing results from execution is according to some pre-determined order, or according to the order in which the results would have been processed during a non-distributed (e.g., sequential) execution, for instance.

Abstract: As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be consistent with the results that would be obtained by executing them in a non-distributed manner. Thus, in one aspect, the algorithms, or portions thereof, have to be made distributable. The algorithms, or portions thereof, are made distributable by isolating any random number generation therewith to be independent of each other. This isolation applies to any random number generation associated with different call instances of the same algorithm as well. In one aspect, the isolation is accomplished by ensuring that the calculation of random number sequences for the algorithms, or portions thereof, is not dependent on random number sequences calculated for the others or between call instances of the same algorithm.

Abstract: A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

Abstract: A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Abstract: Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.

Abstract: A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

Abstract: A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Abstract: Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received comprising entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.

Abstract: Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern.

Abstract: A defect identification tool is disclosed that predicts locations at which defects in a microdevice are most likely to occur. The tool may identify both a type of defect and the particular netlists in which that defect is likely to occur. A test circuit generation tool can then subsequently use this defect information to generate a test circuit that tests for the defect in the identified portions of the microcircuit. Similarly, an automatic test pattern generation tool may use the defect location information to generate test data custom-tailored to check for faults corresponding to the identified defect in the specified portions of the microcircuit. Various implementations of the tool may be used both to identify the locations at which defects caused by systematic errors, such as manufacturing process deficiencies or flaws, are most likely to occur and the locations at which randomly-created defects are most likely to occur.

Abstract: Methods, apparatus, and systems for computing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein, information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported.

Abstract: A scheme for multi-frequency at-speed logic Built-In Self Test (BIST) is provided. This scheme allows at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. The scheme is also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. Scanable memory elements of the digital circuit are connected to define plurality of scan chains. The loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. The BIST controller, Pseudo-Random Pattern Generator (PRPG) and Multi-Input Signature Register (MISR) work at slower frequency than the fastest clock domain. After loading of a new test pattern, a clock suppression circuit allows a scan enable signal to propagate for more that one clock cycle before multiple capture clock is applied.

Abstract: Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, design defect extraction rules are derived at least partially from a set of design manufacturing rules. Potential defects are extracted from a representation of an integrated circuit layout using the design defect extraction rules. Circuit test stimuli applied during one or more circuit tests are determined. Test responses resulting from the applied circuit tests are evaluated to identify integrated circuits that fail and to identify the occurrence in the failing integrated circuits of one or more potential types of defects associated with the applied circuit tests.

Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.

Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, a compactor for compacting test responses in a circuit-under-test is disclosed. In this embodiment, the compactor includes an injector network comprising combinational logic and includes injector-network outputs and injector-network inputs. At least some of the injector-network inputs are logically coupled to two or more injector-network outputs according to respective injector polynomials. The exemplary compactor further comprises a selection circuit that includes selection-circuit outputs coupled to the injector-network inputs and selection-circuit inputs coupled to scan-chain outputs of the circuit-under-test. The selection circuit is configured to selectively route signals from the scan-chain outputs to the injector-network inputs according to one of plural different input configurations.

Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, one or more signatures are received that indicate the presence of one or more errors in one or more corresponding compressed test responses. Scan cells in the circuit-under-test that caused the errors are identified by analyzing the signatures. In this exemplary embodiment, the analysis includes selecting a scan cell candidate that potentially caused an error in a compressed test response based at least partially on a weight value associated with the scan cell candidate, the weight value being indicative of the likelihood that the scan cell candidate caused the error. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided.

Abstract: A scheme for multi-frequency at-speed logic Built-In Self Test (BIST) is provided. This scheme allows at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. The scheme is also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. Scanable memory elements of the digital circuit are connected to define plurality of scan chains. The loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. The BIST controller, Pseudo-Random Pattern Generator (PRPG) and Multi-input Signature Register (MISR) work at slower frequency than the fastest clock domain. After loading of a new test pattern, a clock suppression circuit allows a scan enable signal to propagate for more that one clock cycle before multiple capture clock is applied.