Abstract: A power semiconductor device is provided that includes a depletion mode (normally ON) main switching device cascoded with a higher speed switching device, resulting in an enhancement mode (normally OFF) FET device for switching power applications. The main switching device comprises a depletion mode GaN-based HEMT (High Electron Mobility Transistor) FET that does not include an intrinsic body diode. In one or more embodiments, the higher speed switching device comprises a high speed FET semiconductor switch arranged or connected in parallel with a Schottky diode. The high speed FET semiconductor switch may comprise a Si FET, GaN FET or any other type of FET which possesses higher speed switching capabilities and a lower voltage than that of the GaN-based HEMT FET. In some embodiments, the GaN-based HEMT FET and the higher speed switching device (i.e., the FET and Schottky diode) may be monolithically integrated on the same substrate.

Abstract: A circuit for reducing switching losses in a synchronous rectifier of a switching stage including a high-side control transistor and a low-side synchronous transistor coupled at a switching node, the switching stage receiving an input voltage and providing a controlled output voltage at an output node. The circuit including a first circuit portion for sensing waveshape edges of a first signal at a gate terminal of the low-side synchronous transistor and a first voltage to determine a delay between the waveshape edge of the first signal and the waveshape edge of the first voltage; and a second circuit portion for calibrating the first signal and the first voltage to align the waveshape edge of the first signal and the waveshape edge of the first voltage, with an optional offset to achieve minimal power loss.

Abstract: According to one exemplary embodiment, an efficient and high speed E-mode III-N/Schottky switch includes a silicon transistor coupled with a D-mode III-nitride device, where the silicon transistor causes the D-mode III-nitride device to operate in an enhancement mode. The E-mode III-N/Schottky switch further includes a Schottky diode coupled across the silicon transistor so as to improve efficiency, recovery time, and speed of the E-mode III-N/Schottky switch. An anode of the Schottky diode can be coupled to a source of the silicon transistor and a cathode of the Schottky diode can be coupled to a drain of the silicon transistor. The Schottky diode can be integrated with the silicon transistor. In one embodiment the III-nitride device is a GaN device.

Abstract: A power control system and method including a plurality of point-of-load regulators (POL) providing corresponding regulated output voltages; a manager for communicating control signals and operational parameters with said point-of load regulators; a digital bus to carry control signals therebetween; and an analog bus to carry operational parameters therebetween. Analog sensing circuits and a mutliplexer on the POL communicate operational parameters to and from the manager via the analog bus and are controlled via the digital bus. The operational parameters include output voltage, output current, over voltage, temperature, amplifier or comparator offset, and amplifier gain. The analog sensing circuits are calibrated by trim registers on the POL under digital control by the manager.

Abstract: An integrated circuit that includes a power stage and a driver stage, all stages using III-nitride power devices.

Abstract: A copyright protection method and apparatus employ a first protection scheme within a single authorized domain, in which all interfaces are protected with digital rights management system, and employ a second protection scheme for use in inter-domain file transfers. The method and apparatus employ a third protection scheme for external outputs not protected by a digital rights management system.

Abstract: An interposer electrical interface for placing a DC-DC converter in close proximity with an IC powered by the converter, the DC-DC converter including at least one switching node power supply stage, the at least one switching node power supply stage providing regulated power to the IC, the close proximity of the DC-DC converter and IC allowing for high efficiency in provision of the regulated power from the DC-DC converter to the IC, the interposer electrical interface comprising at least one electrical energy storage element.

Abstract: A circuit for driving a switching stage including control and sync switches series connected at a switching node, at least one of the control and sync switches being a normal ON depletion mode device, the circuit comprising a gate driver including first and second switching stages for generating gate drive signals for the sync and control switches, respectively, the first switching stage having a first driver output node and the second switching stage having a second driver output node, a signal from the first node driving the sync switch and a signal from the second node driving the control switch and a circuit connected to the first and second switching stages, the circuit including a first circuit providing a first voltage source, the first circuit being coupled to the first switching stage and to the sync switch, a first bias voltage from the first voltage source being switched by the first switching stage, the first switching stage having a first state wherein the sync switch is on, and a second state wh

Abstract: A method of improving the operation of a synchronous rectifier circuit which includes a switching transistor and synchronous transistor, by providing an operatively effective value of inductance in the current path of the synchronous transistor; which is shared by the control terminal circuit path of the transistor and by selecting a synchronous transistor having a low resistance to a control signal provided at the control terminal, as well as improved synchronous rectifier circuits designed according to the method. When the transistors are MOSFETs, the inductance provided is preferably a purely parasitic common source inductance in the range of about 2 nH to about 3 nH. The synchronous transistor exhibits a low value of gate resistance to facilitate fast energy exchange between the common source inductance and the gate-source capacitance.

Abstract: A circuit for reducing switching losses in a synchronous rectifier of a switching stage including a high-side control transistor and a low-side synchronous transistor coupled at a switching node, the switching stage receiving an input voltage and providing a controlled output voltage at an output node. The circuit including a first circuit portion for sensing waveshape edges of a first signal at a gate terminal of the low-side synchronous transistor and a first voltage to determine a delay between the waveshape edge of the first signal and the waveshape edge of the first voltage; and a second circuit portion for calibrating the first signal and the first voltage to align the waveshape edge of the first signal and the waveshape edge of the first voltage, with an optional offset to achieve minimal power loss.

Abstract: The high side or low side FET of a buck converter, or both, are replaced by plural parallel devices of different threshold voltage and are turned on and off in a sequence which offers the best turn on and turn off characteristics related to high and low threshold voltages. The parallel devices can have the same or different active areas.

Abstract: A method of obtaining an optimized dead time for a synchronous switching power supply comprising a control IC and two series-connected switches, comprising packaging the control IC and the series-connected switches in a co-packaged module; providing a dead time delay circuit within the control IC circuit which has variable dead time; testing the switching power supply; varying the dead time in a defined sequence during the step of testing; monitoring a parameter during testing of the switching power supply as the dead time is varied; determining an optimal dead time based upon monitoring the parameter; and setting the dead time at the optimal dead time.

Abstract: A power converter driver that is supplied with two different voltages.

Abstract: An article includes a mounting substrate, a passive component site on the mounting substrate, and an active component site on the mounting substrate. The article also includes a fluid flow barrier disposed local to the passive component site and spaced apart from the active component site. The fluid flow barrier can be a recess that resists fluid flow thereinto because of surface tension of the fluid when it meets-the recess edge. The fluid flow barrier can include a boundary that diverts fluid flow due to the angle of the recess edge as the fluid approaches it. An embodiment also includes a packaging system that includes the article and at least one passive component. An embodiment also includes a method of assembling the article or the packaging system.

Abstract: A buck converter circuit is disclosed in which one or both of the control switch and the synchronous switch are III-nitride-based depletion mode. An enhancement mode switch is connected with one or both of the III-nitride based switches and operated to prevent conduction of current by the III-nitride based switch until all biases are established for proper operation.

Abstract: An integrated voltage regulator may be provided on the bottom of a ball grid array processor package. This may be done despite the fact that conventionally integrated voltage regulator chips are too thick to fit in the area normally available between the motherboard and the ball grid array package because that area is defined by solder balls of a necessarily limited height which is conventionally believed to be too small to accommodate the integrated voltage regulator.

Abstract: An article includes a mounting substrate, a passive component site on the mounting substrate, and an active component site on the mounting substrate. The article also includes a fluid flow barrier disposed local to the passive component site and spaced apart from the active component site. The fluid flow barrier can be a recess that resists fluid flow thereinto because of surface tension of the fluid when it meets the recess edge. The fluid flow barrier can include a boundary that diverts fluid flow due to the angle of the recess edge as the fluid approaches it. An embodiment also includes a packaging system that includes the article and at least one passive component. An embodiment also includes a method of assembling the article or the packaging system.

Abstract: Novel fenicol compounds having useful properties as antibiotic prodrugs, are provided, together with methods of making and using these new compounds.

Abstract: An electronic structure includes an electronic device coupled to a substrate by conductive bumps and ball limiting metallurgy (BLM). Underfill material having filler particles is disposed in a space between the electronic device and the substrate. A weight percentage of the filler particles is at least about 60%. A particle size of at least 90 wt % of the filler particles is less than about 2 ?m and/or the filler particles are coated by an organic coupling agent. Once the underfill material is fully cured, its coefficient of thermal expansion is no more than 30 PPM/° C., and its glass transition temperature is at least 100° C., and its adhesion to a passivation layer of the electronic device, to the substrate and to the electronic device at its edges is such that the electronic structure passes standardized reliability tests without delamination of the ball limiting metallurgy.

Abstract: A power control system and method including a plurality of point-of-load regulators (POL) providing corresponding regulated output voltages; a manager for communicating control signals and operational parameters with said point-of load regulators; a digital bus to carry control signals therebetween; and an analog bus to carry operational parameters therebetween. Analog sensing circuits and a mutliplexer on the POL communicate operational parameters to and from the manager via the analog bus and are controlled via the digital bus. The operational parameters include output voltage, output current, over voltage, temperature, amplifier or comparator offset, and amplifier gain. The analog sensing circuits are calibrated by trim registers on the POL under digital control by the manager.